ARM: Update stats for the previous changes and add ARM_FS/O3 regression.

3 files changed, 112 insertions, 105 deletions

diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 3f9e59a85..8dc825ce6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index ba8cd6dca..ffc182a84 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:27:01
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -29,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2431420115000 because target called exit()
+Exiting @ tick 2431419954000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 923e9c734..f32aabd92 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 495941                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237232                       # Number of bytes of host memory used
-host_seconds                                  3435.10                       # Real time elapsed on the host
-host_tick_rate                              707817123                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 781303                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 254132                       # Number of bytes of host memory used
+host_seconds                                  2197.96                       # Real time elapsed on the host
+host_tick_rate                             1106217790                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1703605163                       # Number of instructions simulated
+sim_insts                                  1717270343                       # Number of instructions simulated
 sim_seconds                                  2.431420                       # Number of seconds simulated
-sim_ticks                                2431420115000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          482384248                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.094748                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.094748                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              475158152                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   177141202000                       # number of ReadReq miss cycles
+sim_ticks                                2431419954000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7226096                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155462914000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7226096                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         172586108                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             170696959                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
@@ -30,49 +34,49 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # m
 system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  70.854389                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           654970356                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26435.430315                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               645855111                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    240965424000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9115245                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 213619689000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9115245                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997003                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4083.724785                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          654970356                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26435.430315                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              645855111                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   240965424000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              645854938                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9115245                       # number of overall misses
+system.cpu.dcache.overall_misses              9115236                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 213619689000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9115245                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9111149                       # number of replacements
-system.cpu.dcache.sampled_refs                9115245                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                9111140                       # number of replacements
+system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4083.724785                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                645855111                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            25922969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  3061986                       # number of writebacks
+system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3061985                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses         1544565415                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1544564777                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1544564961                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       34804000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # ms
 system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               2420947.926332                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1544565415                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1544564777                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
@@ -127,12 +131,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.251403                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            514.872908                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses         1544565415                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1544564777                       # number of overall hits
+system.cpu.icache.overall_hits             1544564961                       # number of overall hits
 system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  638                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      7                       # number of replacements
 system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                514.872908                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1544564777                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses            889908                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7226734                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5417169                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   94097380000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.250399                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1809565                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72382600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250399                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1809565                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         3061986                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             3061986                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   94097172000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3061985                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.788539                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9115883                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6416410                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   140372596000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.296129                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2699473                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 107978920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.296129                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2699473                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 107978760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.296128                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.458608                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.338955                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         15027.674424                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11106.876723                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           9115883                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.458607                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.338956                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               6416410                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  140372596000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.296129                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2699473                       # number of overall misses
+system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 107978920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.296129                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2699473                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2687070                       # number of replacements
-system.cpu.l2cache.sampled_refs               2714388                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2687066                       # number of replacements
+system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26134.551147                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7569176                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          538044067000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1171981                       # number of writebacks
+system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4862840230                       # number of cpu cycles simulated
+system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 4862840230                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    177497944                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_fp_insts                            36                       # number of float instructions
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    27330236                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1703605163                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1523276793                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1523276793                       # number of integer instructions
-system.cpu.num_int_register_reads          5115465619                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1316065727                       # number of times the integer registers were written
-system.cpu.num_load_insts                   485926830                       # Number of load instructions
-system.cpu.num_mem_refs                     660773876                       # number of memory refs
+system.cpu.num_insts                       1717270343                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_int_register_reads          5142795796                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1329730906                       # number of times the integer registers were written
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls