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authorAli Saidi <Ali.Saidi@ARM.com>2010-08-25 19:10:42 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-08-25 19:10:42 -0500
commite6d3fe8a0c02e0692444399e63e6c5ce6c3abd17 (patch)
treec8cc90c2577733fa32cd6250a9488450f65d8335 /tests/long/60.bzip2/ref/arm/linux/simple-timing
parent4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe (diff)
downloadgem5-e6d3fe8a0c02e0692444399e63e6c5ce6c3abd17.tar.xz
ARM: Update regression tests for ldr/str microcode changes.
Diffstat (limited to 'tests/long/60.bzip2/ref/arm/linux/simple-timing')
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-timing/simout6
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt12
2 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index c59cdfaa8..362a504a1 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 25 2010 20:52:35
-M5 revision ffac9df60637 7512 default tip
-M5 started Jul 26 2010 23:53:12
+M5 compiled Aug 24 2010 15:34:40
+M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
+M5 started Aug 24 2010 15:41:22
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 9dc5d12af..46cd1e2af 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1188041 # Simulator instruction rate (inst/s)
-host_mem_usage 205272 # Number of bytes of host memory used
-host_seconds 1420.24 # Real time elapsed on the host
-host_tick_rate 1757384537 # Simulator tick rate (ticks/s)
+host_inst_rate 1693548 # Simulator instruction rate (inst/s)
+host_mem_usage 210380 # Number of bytes of host memory used
+host_seconds 1005.94 # Real time elapsed on the host
+host_tick_rate 2481166849 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1687299939 # Number of instructions simulated
+sim_insts 1703605163 # Number of instructions simulated
sim_seconds 2.495902 # Number of seconds simulated
sim_ticks 2495902189000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
@@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 562275129000 # Cy
system.cpu.l2cache.writebacks 1196151 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4991804378 # number of cpu cycles simulated
-system.cpu.num_insts 1687299939 # Number of instructions executed
+system.cpu.num_insts 1703605163 # Number of instructions executed
system.cpu.num_refs 660773876 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls