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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:31 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:31 -0500 |
| commit | b20e92e1ca36486b9f01fa7df7e8cc8a87d17dcb (patch) | |
| tree | e391e796f376b0401ce34e724bad675b80345b68 /tests/long/60.bzip2/ref/arm/linux/simple-timing | |
| parent | 8af1eeec6f28d9722802bf1588c911711db07ddd (diff) | |
| download | gem5-b20e92e1ca36486b9f01fa7df7e8cc8a87d17dcb.tar.xz | |
ARM: Update stats for previous changes.
Diffstat (limited to 'tests/long/60.bzip2/ref/arm/linux/simple-timing')
4 files changed, 11 insertions, 14 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index 8dc825ce6..b26c9b5f5 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr index cdafa164c..eabe42249 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index ffc182a84..50181b6ce 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:27:01 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:14:16 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index f32aabd92..b09cdeb30 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 781303 # Simulator instruction rate (inst/s) -host_mem_usage 254132 # Number of bytes of host memory used -host_seconds 2197.96 # Real time elapsed on the host -host_tick_rate 1106217790 # Simulator tick rate (ticks/s) +host_inst_rate 536583 # Simulator instruction rate (inst/s) +host_mem_usage 254860 # Number of bytes of host memory used +host_seconds 3200.38 # Real time elapsed on the host +host_tick_rate 759728459 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1717270343 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -249,18 +249,18 @@ system.cpu.numCycles 4862839908 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 4862839908 # Number of busy cycles -system.cpu.num_conditional_control_insts 177497944 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_func_calls 27330236 # number of times a function call or return occured +system.cpu.num_func_calls 27330134 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1717270343 # Number of instructions executed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_int_register_reads 5142795796 # number of times the integer registers were read -system.cpu.num_int_register_writes 1329730906 # number of times the integer registers were written +system.cpu.num_int_register_writes 1329729952 # number of times the integer registers were written system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions |