diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/60.bzip2/ref/arm | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/60.bzip2/ref/arm')
3 files changed, 93 insertions, 104 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index 58d6d5f57..6b81a05a4 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index 04bd91fa3..be9f97c93 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 14:05:19 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:06:16 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -31,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2473217439000 because target called exit() +Exiting @ tick 2431420115000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 92d034701..5855e152d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1470110 # Simulator instruction rate (inst/s) -host_mem_usage 211484 # Number of bytes of host memory used -host_seconds 1158.83 # Real time elapsed on the host -host_tick_rate 2134239180 # Simulator tick rate (ticks/s) +host_inst_rate 1373516 # Simulator instruction rate (inst/s) +host_mem_usage 197324 # Number of bytes of host memory used +host_seconds 1240.32 # Real time elapsed on the host +host_tick_rate 1960310324 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1703605163 # Number of instructions simulated -sim_seconds 2.473217 # Number of seconds simulated -sim_ticks 2473217439000 # Number of ticks simulated +sim_seconds 2.431420 # Number of seconds simulated +sim_ticks 2431420115000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24630.043664 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21630.043664 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24514.094748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.094748 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 177979060000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 177141202000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156300772000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 155462914000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 52467.599202 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49467.599202 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 170586898 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104893749000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.011584 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1999210 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98896119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1999210 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 170696959 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30662.702029 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency -system.cpu.dcache.demand_hits 645745050 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 282872809000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.014085 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9225306 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 26435.430315 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23435.430315 # average overall mshr miss latency +system.cpu.dcache.demand_hits 645855111 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 240965424000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9115245 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 255196891000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014085 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9225306 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 213619689000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9115245 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997054 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4083.932190 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.997003 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4083.724785 # Average occupied blocks per context system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30662.702029 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 26435.430315 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23435.430315 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 645745050 # number of overall hits -system.cpu.dcache.overall_miss_latency 282872809000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.014085 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9225306 # number of overall misses +system.cpu.dcache.overall_hits 645855111 # number of overall hits +system.cpu.dcache.overall_miss_latency 240965424000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9115245 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 255196891000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014085 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9225306 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 213619689000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9115245 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 9111149 # number of replacements system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4083.932190 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.724785 # Cycle average of tags in use system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25923011000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2365751 # number of writebacks +system.cpu.dcache.warmup_cycle 25922969000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 3061986 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 638 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.251186 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 514.428387 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.251403 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 514.872908 # Average occupied blocks per context system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 7 # number of replacements system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 514.428387 # Cycle average of tags in use +system.cpu.icache.tagsinuse 514.872908 # Cycle average of tags in use system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 168141 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 89492416000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.910996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1721008 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68840320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910996 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1721008 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 999241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 46275216000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.471063 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 889908 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35596320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 889908 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5397220 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 95134728000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.253159 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1829514 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73180560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.253159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1829514 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 110061 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51957.950591 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5718544000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 110061 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4402440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 110061 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2365751 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2365751 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 5417169 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 94097380000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.250399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1809565 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 72382600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250399 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1809565 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 3061986 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 3061986 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.511929 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.788539 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 9115883 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5565361 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 184627144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.389487 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3550522 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 6416410 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 140372596000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.296129 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2699473 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 142020880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.389487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3550522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 107978920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.296129 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2699473 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.457042 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.333046 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 14976.359071 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10913.242343 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.458608 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.338955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15027.674424 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11106.876723 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9115883 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5565361 # number of overall hits -system.cpu.l2cache.overall_miss_latency 184627144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.389487 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3550522 # number of overall misses +system.cpu.l2cache.overall_hits 6416410 # number of overall hits +system.cpu.l2cache.overall_miss_latency 140372596000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.296129 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2699473 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 142020880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.389487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3550522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 107978920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.296129 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2699473 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2702712 # number of replacements -system.cpu.l2cache.sampled_refs 2729930 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2687070 # number of replacements +system.cpu.l2cache.sampled_refs 2714388 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25889.601414 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6857391 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 555158623000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1177576 # number of writebacks +system.cpu.l2cache.tagsinuse 26134.551147 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7569176 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 538044067000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1171981 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4946434878 # number of cpu cycles simulated +system.cpu.numCycles 4862840230 # number of cpu cycles simulated system.cpu.num_insts 1703605163 # Number of instructions executed system.cpu.num_refs 660773876 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls |