diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-05-03 00:45:01 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-05-03 00:45:01 -0700 |
| commit | 8b0c83008e6c1964c9606a47213f11599ab186c5 (patch) | |
| tree | b15e4205be5850c21bcfa241b548173cb8a088b7 /tests/long/60.bzip2/ref/x86/linux | |
| parent | 2ee7a892092086db1bdf707438a9c10bf1426a69 (diff) | |
| download | gem5-8b0c83008e6c1964c9606a47213f11599ab186c5.tar.xz | |
X86: Update stats for the updated auxilliary vectors.
Diffstat (limited to 'tests/long/60.bzip2/ref/x86/linux')
6 files changed, 138 insertions, 138 deletions
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index d7e2d0edd..8cd09b7fa 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 84cb84ccc..64c167284 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:41:05 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:57:51 -M5 executing on SC2B0619 +M5 compiled May 2 2010 23:23:01 +M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch +M5 started May 2 2010 23:23:02 +M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2829239875500 because target called exit() +Exiting @ tick 2829239906500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 46cb78389..e93b432fd 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1880958 # Simulator instruction rate (inst/s) -host_mem_usage 188832 # Number of bytes of host memory used -host_seconds 2473.91 # Real time elapsed on the host -host_tick_rate 1143628848 # Simulator tick rate (ticks/s) +host_inst_rate 2905658 # Simulator instruction rate (inst/s) +host_mem_usage 217444 # Number of bytes of host memory used +host_seconds 1601.47 # Real time elapsed on the host +host_tick_rate 1766650252 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653327894 # Number of instructions simulated +sim_insts 4653327945 # Number of instructions simulated sim_seconds 2.829240 # Number of seconds simulated -sim_ticks 2829239875500 # Number of ticks simulated +sim_ticks 2829239906500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5658479752 # number of cpu cycles simulated -system.cpu.num_insts 4653327894 # Number of instructions executed -system.cpu.num_refs 1677713078 # Number of memory references +system.cpu.numCycles 5658479814 # number of cpu cycles simulated +system.cpu.num_insts 4653327945 # Number of instructions executed +system.cpu.num_refs 1677713086 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index 734089aa9..9d193ac5e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 8794a16bf..627d9abd2 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:41:05 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:58:19 -M5 executing on SC2B0619 +M5 compiled May 2 2010 23:23:01 +M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch +M5 started May 2 2010 23:23:02 +M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5988037845000 because target called exit() +Exiting @ tick 5988071419000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index d56c14beb..63b5e7379 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,82 +1,82 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1049992 # Simulator instruction rate (inst/s) -host_mem_usage 196480 # Number of bytes of host memory used -host_seconds 4431.78 # Real time elapsed on the host -host_tick_rate 1351159917 # Simulator tick rate (ticks/s) +host_inst_rate 1729585 # Simulator instruction rate (inst/s) +host_mem_usage 225072 # Number of bytes of host memory used +host_seconds 2690.43 # Real time elapsed on the host +host_tick_rate 2225692892 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653327894 # Number of instructions simulated -sim_seconds 5.988038 # Number of seconds simulated -sim_ticks 5988037845000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25018.463901 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22018.463901 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1231962487 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 180689726000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005828 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7222255 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159022961000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005828 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222255 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.840680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.840680 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 436281288 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125834330000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247048 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119093186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247048 # number of WriteReq MSHR misses +sim_insts 4653327945 # Number of instructions simulated +sim_seconds 5.988071 # Number of seconds simulated +sim_ticks 5988071419000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25017.777193 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.777193 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180699652000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159031102000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.839821 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839821 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436280849 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125858968000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005125 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247488 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119116504000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005125 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247488 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.121439 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32370.287021 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668243775 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 306524056000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005644 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9469303 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32370.399029 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668242748 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306558620000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470338 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 278116147000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005644 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9469303 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 278147606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470338 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997259 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4084.774232 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32370.287021 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997262 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4084.783575 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32370.399029 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668243775 # number of overall hits -system.cpu.dcache.overall_miss_latency 306524056000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005644 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9469303 # number of overall misses +system.cpu.dcache.overall_hits 1668242748 # number of overall hits +system.cpu.dcache.overall_miss_latency 306558620000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470338 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 278116147000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005644 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9469303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 278147606000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470338 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9107896 # number of replacements -system.cpu.dcache.sampled_refs 9111992 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9108581 # number of replacements +system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.774232 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668601086 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58863918000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2243955 # number of writebacks -system.cpu.icache.ReadReq_accesses 4013232890 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tagsinuse 4084.783575 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58864073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244395 # number of writebacks +system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4013232215 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5945529.207407 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4013232890 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4013232215 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 555.573148 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 555.572992 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4013232215 # number of overall hits +system.cpu.icache.overall_hits 4013232252 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.573148 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232215 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.572992 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889737 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98266324000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 98271004000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889737 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75589480000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1889827 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75593080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889737 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7222930 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 1889827 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5327537 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 98560436000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.262413 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1895393 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75815720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262413 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1895393 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 357311 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.899729 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 5328094 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98562412000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262397 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895431 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75817240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895431 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357661 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.659935 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18561556000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 18579652000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 357311 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14292440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 357661 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14306440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 357311 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2243955 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2243955 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 357661 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244395 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244395 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.380966 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.381264 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9112667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5327537 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 196826760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415370 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3785130 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5328094 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196833416000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415353 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785258 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 151405200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3785130 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 151410320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415353 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785258 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.437806 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.347809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 14346.014207 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11397.001683 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 9112667 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.437808 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.347808 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 14346.083027 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11396.963852 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5327537 # number of overall hits -system.cpu.l2cache.overall_miss_latency 196826760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415370 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3785130 # number of overall misses +system.cpu.l2cache.overall_hits 5328094 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196833416000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415353 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785258 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 151405200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3785130 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 151410320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415353 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785258 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2771977 # number of replacements -system.cpu.l2cache.sampled_refs 2798150 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2772035 # number of replacements +system.cpu.l2cache.sampled_refs 2798208 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25743.015890 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6662299 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4737770578000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1199166 # number of writebacks +system.cpu.l2cache.tagsinuse 25743.046878 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6663271 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4737794502000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199204 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11976075690 # number of cpu cycles simulated -system.cpu.num_insts 4653327894 # Number of instructions executed -system.cpu.num_refs 1677713078 # Number of memory references +system.cpu.numCycles 11976142838 # number of cpu cycles simulated +system.cpu.num_insts 4653327945 # Number of instructions executed +system.cpu.num_refs 1677713086 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- |