diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/long/60.bzip2/ref | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/long/60.bzip2/ref')
10 files changed, 968 insertions, 967 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 6cb2c5232..e32660b85 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout index a850d490c..1fce660ea 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 08:31:13 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:14:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1016488689500 because target called exit() +Exiting @ tick 1009857089500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index a608e7e97..48a5816be 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.016489 # Number of seconds simulated -sim_ticks 1016488689500 # Number of ticks simulated +sim_seconds 1.009857 # Number of seconds simulated +sim_ticks 1009857089500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111625 # Simulator instruction rate (inst/s) -host_tick_rate 62351436 # Simulator tick rate (ticks/s) -host_mem_usage 193064 # Number of bytes of host memory used -host_seconds 16302.57 # Real time elapsed on the host +host_inst_rate 45175 # Simulator instruction rate (inst/s) +host_tick_rate 25069239 # Simulator tick rate (ticks/s) +host_mem_usage 245844 # Number of bytes of host memory used +host_seconds 40282.72 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614416 # DTB read hits +system.cpu.dtb.read_hits 444614420 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511494 # DTB read accesses -system.cpu.dtb.write_hits 160920901 # DTB write hits +system.cpu.dtb.read_accesses 449511498 # DTB read accesses +system.cpu.dtb.write_hits 160920903 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622205 # DTB write accesses -system.cpu.dtb.data_hits 605535317 # DTB hits +system.cpu.dtb.write_accesses 162622207 # DTB write accesses +system.cpu.dtb.data_hits 605535323 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133699 # DTB accesses -system.cpu.itb.fetch_hits 237932826 # ITB hits +system.cpu.dtb.data_accesses 612133705 # DTB accesses +system.cpu.itb.fetch_hits 233080732 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 237932848 # ITB accesses +system.cpu.itb.fetch_accesses 233080754 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2032977380 # number of cpu cycles simulated +system.cpu.numCycles 2019714180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1759886457 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 440243372 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1592734008 # Number of cycles cpu stages are processed. -system.cpu.activity 78.344896 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed. +system.cpu.activity 78.072669 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -61,85 +61,85 @@ system.cpu.comFloats 190 # Nu system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) -system.cpu.cpi 1.117156 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.117156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.895131 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.895131 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 338882102 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 262365824 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 145832523 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 223761389 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 153206045 # Number of BTB hits +system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 68.468490 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 189687399 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 149194703 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667621622 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043824239 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 226 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 571 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 655476684 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617179738 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 132311663 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 6922402 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 139234065 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 75965071 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 64.700104 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1137833135 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617252269 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 823371490 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1209605890 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.499230 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1094712452 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 938264928 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.152256 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1056818268 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 976159112 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.016231 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1623201304 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409776076 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.156450 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1008711848 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1024265532 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.382535 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 664.417711 # Cycle average of tags in use -system.cpu.icache.total_refs 237931761 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use +system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277309.744755 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 664.417711 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324423 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 237931761 # number of ReadReq hits -system.cpu.icache.demand_hits 237931761 # number of demand (read+write) hits -system.cpu.icache.overall_hits 237931761 # number of overall hits +system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits +system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits +system.cpu.icache.overall_hits 233079667 # number of overall hits system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses system.cpu.icache.overall_misses 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 58372500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 58372500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 58372500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 237932823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 237932823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 237932823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54964.689266 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54964.689266 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 81000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks @@ -150,97 +150,97 @@ system.cpu.icache.ReadReq_mshr_misses 858 # nu system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45874500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45874500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45874500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53466.783217 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.698985 # Cycle average of tags in use -system.cpu.dcache.total_refs 595070238 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use +system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310172 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12613555000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.698985 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996753 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437271427 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 157798811 # number of WriteReq hits -system.cpu.dcache.demand_hits 595070238 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 595070238 # number of overall hits -system.cpu.dcache.ReadReq_misses 7324236 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 2929691 # number of WriteReq misses -system.cpu.dcache.demand_misses 10253927 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 10253927 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 180890019000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110280256500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 291170275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 291170275500 # number of overall miss cycles +system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits +system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 595070081 # number of overall hits +system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses +system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 10254084 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.018228 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24697.459093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37642.282582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 28395.977024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 28395.977024 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10999500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8090380500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208980 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.882651 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38713.659202 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 101954 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1040525 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1142479 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1142479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156087353000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 59191861000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215279214000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215279214000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.916151 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.270960 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686299 # number of replacements -system.cpu.l2cache.tagsinuse 26362.253179 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 225759748000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15507.582634 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10854.670545 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.473254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.331258 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits @@ -250,10 +250,10 @@ system.cpu.l2cache.ReadReq_misses 1807881 # nu system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94453448000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46507349000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140960797000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140960797000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses) @@ -263,10 +263,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.250305 # mi system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52245.390045 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.050659 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52262.752692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -283,19 +283,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 889275 # nu system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72354306000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108025392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108025392000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.608723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.547862 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 73cbafb08..d0874930c 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 96ed5aa20..ffc7fc253 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:58:23 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:16:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 701966325500 because target called exit() +Exiting @ tick 635013348500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index ebab377c0..dda342878 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.701966 # Number of seconds simulated -sim_ticks 701966325500 # Number of ticks simulated +sim_seconds 0.635013 # Number of seconds simulated +sim_ticks 635013348500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187255 # Simulator instruction rate (inst/s) -host_tick_rate 75716158 # Simulator tick rate (ticks/s) -host_mem_usage 193592 # Number of bytes of host memory used -host_seconds 9271.02 # Real time elapsed on the host +host_inst_rate 68058 # Simulator instruction rate (inst/s) +host_tick_rate 24894495 # Simulator tick rate (ticks/s) +host_mem_usage 246392 # Number of bytes of host memory used +host_seconds 25508.18 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 563960671 # DTB read hits -system.cpu.dtb.read_misses 9341526 # DTB read misses +system.cpu.dtb.read_hits 603338361 # DTB read hits +system.cpu.dtb.read_misses 10295627 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 573302197 # DTB read accesses -system.cpu.dtb.write_hits 197357333 # DTB write hits -system.cpu.dtb.write_misses 6267768 # DTB write misses +system.cpu.dtb.read_accesses 613633988 # DTB read accesses +system.cpu.dtb.write_hits 208599183 # DTB write hits +system.cpu.dtb.write_misses 6680918 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 203625101 # DTB write accesses -system.cpu.dtb.data_hits 761318004 # DTB hits -system.cpu.dtb.data_misses 15609294 # DTB misses +system.cpu.dtb.write_accesses 215280101 # DTB write accesses +system.cpu.dtb.data_hits 811937544 # DTB hits +system.cpu.dtb.data_misses 16976545 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 776927298 # DTB accesses -system.cpu.itb.fetch_hits 346935606 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 828914089 # DTB accesses +system.cpu.itb.fetch_hits 391544242 # ITB hits +system.cpu.itb.fetch_misses 36 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 346935639 # ITB accesses +system.cpu.itb.fetch_accesses 391544278 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1403932652 # number of cpu cycles simulated +system.cpu.numCycles 1270026698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits +system.cpu.BPredUnit.lookups 374312464 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 289169438 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19496445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 340941395 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 334345011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed -system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 24666648 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1937 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 404704037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3147798119 # Number of instructions fetch has processed +system.cpu.fetch.Branches 374312464 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 359011659 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 616794499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137998027 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 125668111 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391544242 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8927962 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1258617999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.500996 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.012045 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 848087817 60.78% 60.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47124000 3.38% 64.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30216424 2.17% 66.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 49573099 3.55% 69.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 121201096 8.69% 78.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 67474425 4.84% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44590738 3.20% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37036211 2.65% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 149944946 10.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 641823500 50.99% 50.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53319636 4.24% 55.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35799554 2.84% 58.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 54964384 4.37% 62.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137079474 10.89% 73.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 75209346 5.98% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 52974044 4.21% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 43807155 3.48% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 163640906 13.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1258617999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.294728 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.478529 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434225808 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112156946 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 585871640 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14914010 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111449595 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58364893 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 867 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3066482661 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1948 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111449595 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456759816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 64512146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 4249 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 576631270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49260923 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2982899565 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 509098 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7685931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 38326944 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2232338965 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3854814610 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3853783957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1030653 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 856136002 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 193 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 190 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103200080 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 676333170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252017068 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 107962644 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 56514638 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2687392423 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 179 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2469741583 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1752104 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 940434860 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416211296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 150 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1258617999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.962265 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.926131 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 411515074 32.70% 32.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 202456949 16.09% 48.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202249342 16.07% 64.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156364195 12.42% 77.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 139152023 11.06% 88.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73667183 5.85% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48795801 3.88% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19364904 1.54% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5052528 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1258617999 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3576452 24.84% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9406298 65.33% 90.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1415397 9.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617611726 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 92 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 252 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 146 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 18 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 631548427 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 220580878 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued -system.cpu.iq.rate 1.640295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2469741583 # Type of FU issued +system.cpu.iq.rate 1.944638 # Inst issue rate +system.cpu.iq.fu_busy_cnt 14398147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005830 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6212471762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3627257196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2370962102 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1779654 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1040695 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 834376 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2483251910 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 887820 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52535371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 231737507 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 276679 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 497053 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91288566 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 59 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 156775 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 111449595 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23764552 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1337877 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2830649403 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12818049 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 676333170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252017068 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 179 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 569958 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 21987 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 497053 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 20334660 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2042240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22376900 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2418005225 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 613634241 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 51736358 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 128264130 # number of nop insts executed -system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed -system.cpu.iew.exec_branches 278210520 # Number of branches executed -system.cpu.iew.exec_stores 203625107 # Number of stores executed -system.cpu.iew.exec_rate 1.613458 # Inst execution rate -system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1225810379 # num instructions producing a value -system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value +system.cpu.iew.exec_nop 143256801 # number of nop insts executed +system.cpu.iew.exec_refs 828914361 # number of memory reference insts executed +system.cpu.iew.exec_branches 295415710 # Number of branches executed +system.cpu.iew.exec_stores 215280120 # Number of stores executed +system.cpu.iew.exec_rate 1.903901 # Inst execution rate +system.cpu.iew.wb_sent 2397586638 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2371796478 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1365189773 # num instructions producing a value +system.cpu.iew.wb_consumers 1727887810 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back +system.cpu.iew.wb_rate 1.867517 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790092 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 780151578 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19495666 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147168404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.586323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.463059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 609653045 53.14% 53.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194676784 16.97% 70.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91786029 8.00% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52706326 4.59% 82.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37714625 3.29% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27440530 2.39% 88.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24523987 2.14% 90.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21129390 1.84% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 87537688 7.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1147168404 # Number of insts commited each cycle system.cpu.commit.count 1819780126 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 605324165 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 87537688 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3541690829 # The number of ROB reads -system.cpu.rob.rob_writes 4844528665 # The number of ROB writes -system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3573783220 # The number of ROB reads +system.cpu.rob.rob_writes 5311487808 # The number of ROB writes +system.cpu.timesIdled 516531 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11408699 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads -system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads -system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes -system.cpu.fp_regfile_reads 788 # number of floating regfile reads -system.cpu.fp_regfile_writes 457 # number of floating regfile writes +system.cpu.cpi 0.731564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.731564 # CPI: Total CPI of All Threads +system.cpu.ipc 1.366935 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.366935 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3252607111 # number of integer regfile reads +system.cpu.int_regfile_writes 1898786107 # number of integer regfile writes +system.cpu.fp_regfile_reads 15156 # number of floating regfile reads +system.cpu.fp_regfile_writes 507 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use -system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 750.127276 # Cycle average of tags in use +system.cpu.icache.total_refs 391542886 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 415209.847296 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits -system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits -system.cpu.icache.overall_hits 346934350 # number of overall hits -system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses -system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1256 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency +system.cpu.icache.occ_blocks::0 750.127276 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.366273 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 391542886 # number of ReadReq hits +system.cpu.icache.demand_hits 391542886 # number of demand (read+write) hits +system.cpu.icache.overall_hits 391542886 # number of overall hits +system.cpu.icache.ReadReq_misses 1356 # number of ReadReq misses +system.cpu.icache.demand_misses 1356 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1356 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47427000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47427000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47427000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 391544242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 391544242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 391544242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34975.663717 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34975.663717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34975.663717 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33462000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35484.623542 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9157179 # number of replacements -system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use -system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits +system.cpu.dcache.replacements 9159383 # number of replacements +system.cpu.dcache.tagsinuse 4087.248136 # Cycle average of tags in use +system.cpu.dcache.total_refs 696439531 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9163479 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.001651 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5155151000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.248136 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997863 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 540576764 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 155862765 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 670151455 # number of overall hits -system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses +system.cpu.dcache.demand_hits 696439529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 696439529 # number of overall hits +system.cpu.dcache.ReadReq_misses 10153388 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4865737 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 14741918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15019125 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15019125 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 168572903500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 135364757471 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 303937660971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 303937660971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 550730152 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 711458654 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 711458654 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.018436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030273 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.021110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16602.625990 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27819.990573 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 20236.708928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20236.708928 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 117209937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148380000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37031 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65114 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3165.184224 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32994.133366 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3077964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 3077410 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2875087 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2980560 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5855647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5855647 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7278301 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1885177 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 9163478 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9163478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 80739671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38395339625 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 119135011125 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 119135011125 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013216 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011729 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.012880 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.012880 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11093.203139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20366.967996 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2693244 # number of replacements -system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6458351 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2703837 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2693761 # number of replacements +system.cpu.l2cache.tagsinuse 26701.570875 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7632488 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2718396 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.807717 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 128397458500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15961.645382 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10739.925493 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487111 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327757 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5458441 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3077410 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1001668 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6460109 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6460109 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1820800 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 883513 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2704313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2704313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 62491098500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 30447807000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 92938905500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 92938905500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7279241 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3077410 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1885181 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9164422 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9164422 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.468662 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295088 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295088 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34320.682392 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34462.205989 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34366.918881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34366.918881 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 17342500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1668 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10397.182254 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171773 # number of writebacks +system.cpu.l2cache.writebacks 1171800 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1820800 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 883513 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2704313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2704313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56720900500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27626952000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 84347852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 84347852500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468662 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295088 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295088 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.636918 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.434632 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 2386e9fa4..9b272f457 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 2decff9a6..fe3177229 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 19:27:10 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 03:49:53 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -30,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 566011920000 because target called exit() +Exiting @ tick 524441606000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 974fb936f..f09bdc94a 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.566012 # Number of seconds simulated -sim_ticks 566011920000 # Number of ticks simulated +sim_seconds 0.524442 # Number of seconds simulated +sim_ticks 524441606000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52057 # Simulator instruction rate (inst/s) -host_tick_rate 17100212 # Simulator tick rate (ticks/s) -host_mem_usage 255500 # Number of bytes of host memory used -host_seconds 33099.70 # Real time elapsed on the host -sim_insts 1723073884 # Number of instructions simulated +host_inst_rate 101251 # Simulator instruction rate (inst/s) +host_tick_rate 30817067 # Simulator tick rate (ticks/s) +host_mem_usage 257952 # Number of bytes of host memory used +host_seconds 17017.90 # Real time elapsed on the host +sim_insts 1723073904 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1132023841 # number of cpu cycles simulated +system.cpu.numCycles 1048883213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 287218932 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 236434259 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18348095 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 250920104 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 213740165 # Number of BTB hits +system.cpu.BPredUnit.lookups 317450426 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 259852467 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18436703 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 279904663 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 254677721 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18278609 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 393 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 265451297 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2081730004 # Number of instructions fetch has processed -system.cpu.fetch.Branches 287218932 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 232018774 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452716467 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20281434 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 265451297 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5801201 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1120688032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.061143 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.942664 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 20220648 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 4428 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 315501768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2280935015 # Number of instructions fetch has processed +system.cpu.fetch.Branches 317450426 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 274898369 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 509081814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 103935328 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 124227879 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 270 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 303015456 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6379891 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1031116877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.459992 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.013809 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 667971623 59.60% 59.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32961041 2.94% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 55903718 4.99% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56895013 5.08% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 45557119 4.07% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54242890 4.84% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 48750643 4.35% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18749981 1.67% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 139656004 12.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 522035116 50.63% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 37818104 3.67% 54.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 65533745 6.36% 60.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 69512456 6.74% 67.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 53414736 5.18% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61047606 5.92% 78.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 57075579 5.54% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19670108 1.91% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 145009427 14.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1120688032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.253722 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.838945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 546126816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71463989 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 435974123 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6702645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60420459 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 43189829 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 635 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2259641783 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2302 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60420459 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 563998095 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40175582 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14256 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 424146965 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 31932675 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2194117520 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11722 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3482918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25684334 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2171048745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10125608138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10125607580 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 558 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 464728733 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 629 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66642282 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 598549667 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 212535274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87730642 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 84698913 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112468775 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1975042527 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 852567 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 380766314 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 858455180 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1120688032 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.762348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.680120 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1031116877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.302656 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.174632 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 346461175 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106173290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 477865699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18312225 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 82304488 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 48528259 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2473135818 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2289 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 82304488 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 368931509 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50902781 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20077 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 472181274 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56776748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2411760057 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18939 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5901279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 44092765 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2386823429 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 11134835710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11134834246 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1464 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320039 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 680503385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 848 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 119214990 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 651763451 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 230362141 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 123114303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 108844207 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2285934828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 851 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2067906375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3040241 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 557691684 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1352307582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 383 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1031116877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.005501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.810247 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 337912961 30.15% 30.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 234234895 20.90% 51.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 220010483 19.63% 70.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141420525 12.62% 83.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 101836492 9.09% 92.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 53894209 4.81% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 20983167 1.87% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9353324 0.83% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1041976 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 302093175 29.30% 29.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 161453829 15.66% 44.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185974655 18.04% 62.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152722281 14.81% 77.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 122859599 11.92% 89.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 63855935 6.19% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30343304 2.94% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10954294 1.06% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 859805 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1120688032 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1031116877 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 517494 2.12% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 23433886 96.11% 98.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 430313 1.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 735734 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 145 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17865428 91.35% 95.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 956298 4.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219473147 61.74% 61.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1083372 0.05% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 566098039 28.66% 90.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 188387953 9.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1267972738 61.32% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1165735 0.06% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 9 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 605808033 29.30% 90.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192959848 9.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1975042527 # Type of FU issued -system.cpu.iq.rate 1.744700 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24381694 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5096007233 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2495143403 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1922135162 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 114 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1999424161 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 34829517 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2067906375 # Type of FU issued +system.cpu.iq.rate 1.971532 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19557605 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009458 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5189527225 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2846700346 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1993811028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 105 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2087463854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 48700640 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 112622888 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 463072 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1914554 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37688221 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 165836668 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 182984 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3082033 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55515084 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 273360 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451401 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60420459 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18632955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1195402 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112469674 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6157143 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 598549667 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 212535274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 546 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 334650 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1914554 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 16889121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3256921 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20146042 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1946822051 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 556717785 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 28220476 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 82304488 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22549936 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1320929 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286019853 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6521602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 651763451 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 230362141 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 777 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 333118 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 65136 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3082033 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18892989 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1847041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 20740030 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2026288483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 583345448 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 41617892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 283 # number of nop insts executed -system.cpu.iew.exec_refs 742905406 # number of memory reference insts executed -system.cpu.iew.exec_branches 235411550 # Number of branches executed -system.cpu.iew.exec_stores 186187621 # Number of stores executed -system.cpu.iew.exec_rate 1.719771 # Inst execution rate -system.cpu.iew.wb_sent 1926889510 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1922135210 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1211916900 # num instructions producing a value -system.cpu.iew.wb_consumers 1896005064 # num instructions consuming a value +system.cpu.iew.exec_nop 84174 # number of nop insts executed +system.cpu.iew.exec_refs 773137523 # number of memory reference insts executed +system.cpu.iew.exec_branches 241378100 # Number of branches executed +system.cpu.iew.exec_stores 189792075 # Number of stores executed +system.cpu.iew.exec_rate 1.931853 # Inst execution rate +system.cpu.iew.wb_sent 2004592772 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1993811133 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1313765556 # num instructions producing a value +system.cpu.iew.wb_consumers 2094642495 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.697964 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.639195 # average fanout of values written-back +system.cpu.iew.wb_rate 1.900890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.627203 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073902 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 389560093 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 464 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18347567 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1060267574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.338631 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1723073922 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 563083903 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 468 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 18443845 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 948812390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.816032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.570732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 472290035 44.54% 44.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 255203775 24.07% 68.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110318720 10.40% 79.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55061761 5.19% 84.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28404469 2.68% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27943387 2.64% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20897685 1.97% 91.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17855453 1.68% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 72292289 6.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 421119309 44.38% 44.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 219659546 23.15% 67.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 84920332 8.95% 76.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 40130029 4.23% 80.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24924955 2.63% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30334777 3.20% 86.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23612661 2.49% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12752294 1.34% 90.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 91358487 9.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1060267574 # Number of insts commited each cycle -system.cpu.commit.count 1723073902 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 948812390 # Number of insts commited each cycle +system.cpu.commit.count 1723073922 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773831 # Number of memory references committed -system.cpu.commit.loads 485926778 # Number of loads committed +system.cpu.commit.refs 660773839 # Number of memory references committed +system.cpu.commit.loads 485926782 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462372 # Number of branches committed +system.cpu.commit.branches 213462376 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941897 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 72292289 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 91358487 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3100608681 # The number of ROB reads -system.cpu.rob.rob_writes 4285815110 # The number of ROB writes -system.cpu.timesIdled 696063 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11335809 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073884 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073884 # Number of Instructions Simulated -system.cpu.cpi 0.656979 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656979 # CPI: Total CPI of All Threads -system.cpu.ipc 1.522118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.522118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9738255749 # number of integer regfile reads -system.cpu.int_regfile_writes 1902471542 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 2800450937 # number of misc regfile reads -system.cpu.misc_regfile_writes 140 # number of misc regfile writes +system.cpu.rob.rob_reads 3143611129 # The number of ROB reads +system.cpu.rob.rob_writes 4654874733 # The number of ROB writes +system.cpu.timesIdled 997575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17766336 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1723073904 # Number of Instructions Simulated +system.cpu.committedInsts_total 1723073904 # Number of Instructions Simulated +system.cpu.cpi 0.608728 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.608728 # CPI: Total CPI of All Threads +system.cpu.ipc 1.642770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.642770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10134733413 # number of integer regfile reads +system.cpu.int_regfile_writes 1980533280 # number of integer regfile writes +system.cpu.fp_regfile_reads 92 # number of floating regfile reads +system.cpu.fp_regfile_writes 35 # number of floating regfile writes +system.cpu.misc_regfile_reads 3028358925 # number of misc regfile reads +system.cpu.misc_regfile_writes 148 # number of misc regfile writes system.cpu.icache.replacements 9 # number of replacements -system.cpu.icache.tagsinuse 573.017722 # Cycle average of tags in use -system.cpu.icache.total_refs 265450383 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 717 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370223.686192 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 611.010403 # Cycle average of tags in use +system.cpu.icache.total_refs 303014437 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 739 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 410033.067659 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 573.017722 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.279794 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 265450383 # number of ReadReq hits -system.cpu.icache.demand_hits 265450383 # number of demand (read+write) hits -system.cpu.icache.overall_hits 265450383 # number of overall hits -system.cpu.icache.ReadReq_misses 914 # number of ReadReq misses -system.cpu.icache.demand_misses 914 # number of demand (read+write) misses -system.cpu.icache.overall_misses 914 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32210500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32210500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32210500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 265451297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 265451297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 265451297 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 611.010403 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 303014437 # number of ReadReq hits +system.cpu.icache.demand_hits 303014437 # number of demand (read+write) hits +system.cpu.icache.overall_hits 303014437 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35224000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35224000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35224000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 303015456 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 303015456 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 303015456 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35241.247265 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35241.247265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35241.247265 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34567.222767 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34567.222767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34567.222767 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 197 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 197 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 197 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 717 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 717 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 717 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 739 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 739 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24697500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24697500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24697500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25462500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34455.345061 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9552367 # number of replacements -system.cpu.dcache.tagsinuse 4082.984998 # Cycle average of tags in use -system.cpu.dcache.total_refs 675087648 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9556463 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.641999 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6495236000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.984998 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996823 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 507131941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167955564 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 69 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 675087505 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 675087505 # number of overall hits -system.cpu.dcache.ReadReq_misses 10254687 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4630483 # number of WriteReq misses +system.cpu.dcache.replacements 9572098 # number of replacements +system.cpu.dcache.tagsinuse 4088.159469 # Cycle average of tags in use +system.cpu.dcache.total_refs 687277052 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9576194 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 71.769333 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3603059000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4088.159469 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998086 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 519599165 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 167677732 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 82 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 73 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 687276897 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 687276897 # number of overall hits +system.cpu.dcache.ReadReq_misses 10430920 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4908315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 14885170 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 14885170 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 173914872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 112892331168 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15339235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15339235 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 181621482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 122280886057 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 286807203168 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 286807203168 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 517386628 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 303902368057 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 303902368057 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 530030085 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 69 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 689972675 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 689972675 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.026830 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021574 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021574 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 85 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 73 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 702616132 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 702616132 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.019680 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.028440 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.035294 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.021832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 17411.837307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24913.007021 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19267.983044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19267.983044 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 148361910 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35813 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4142.683104 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 19812.094153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19812.094153 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267003640 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 90682 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2944.395139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21777.777778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3126452 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2590385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2738322 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 3128448 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2747497 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3015544 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5328707 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5328707 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7664302 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892161 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9556463 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9556463 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 5763041 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5763041 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7683423 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1892771 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9576194 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9576194 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 89320855000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 42428124877 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 131748979877 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 131748979877 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 90753159500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 45245223293 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 135998382793 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 135998382793 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013850 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013850 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014496 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.013629 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.013629 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11811.553197 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23904.224702 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2920822 # number of replacements -system.cpu.l2cache.tagsinuse 26404.864855 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7838163 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2948145 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.658676 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 129803245500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15746.128543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10658.736312 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.480534 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.325279 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5643332 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3126452 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980638 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6623970 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6623970 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2021685 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 911525 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2933210 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2933210 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69338469500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31601923000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 100940392500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 100940392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7665017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3126452 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9557180 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9557180 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263755 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.481737 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.306912 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.306912 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34412.944351 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34412.944351 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 48964500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2927988 # number of replacements +system.cpu.l2cache.tagsinuse 26803.816569 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7852126 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2955312 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.656953 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 105427800500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15979.704689 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10824.111881 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.330326 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5656220 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3128448 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 980310 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6636530 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6636530 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2027940 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 912463 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2940403 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2940403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 69613457000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 31659273500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 101272730500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 101272730500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7684160 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3128448 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1892773 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9576933 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9576933 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.263912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.482077 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.307030 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.307030 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.177826 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.501118 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34441.785871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34441.785871 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 56425500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 5689 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6606 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8606.872913 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8541.553134 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1216359 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2021675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 911525 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2933200 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2933200 # number of overall MSHR misses +system.cpu.l2cache.writebacks 1217599 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2027928 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 912463 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2940391 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2940391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 62968532000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28735558500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 91704090500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 91704090500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 63193895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28814819500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 92008714500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 92008714500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263753 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481737 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.306911 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.306911 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263910 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482077 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.307028 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.307028 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.804068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.164854 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |