diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/60.bzip2/ref | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/60.bzip2/ref')
25 files changed, 471 insertions, 467 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 95d2d20dc..6cb2c5232 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout index febae9611..6c62eaee3 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2011 03:06:45 -M5 revision baf4b5f6782e 8094 default tip -M5 started Feb 27 2011 03:13:10 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 68c508b83..3b06d5b45 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 121455 # Simulator instruction rate (inst/s) -host_mem_usage 1130520 # Number of bytes of host memory used -host_seconds 14983.11 # Real time elapsed on the host -host_tick_rate 65403738 # Simulator tick rate (ticks/s) +host_inst_rate 191712 # Simulator instruction rate (inst/s) +host_mem_usage 1122860 # Number of bytes of host memory used +host_seconds 9492.28 # Real time elapsed on the host +host_tick_rate 103236678 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.979951 # Number of seconds simulated sim_ticks 979951369500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 614316005 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 69.872947 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 82064192 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 117447733 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 79224651 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 175157411 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 253574750 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 1162207758 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 135407901 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 75 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 1801820745 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 1376202963 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic system.cpu.activity 74.309805 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 614316005 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 69.872947 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 82064192 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 117447733 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 79224651 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 175157411 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 253574750 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.comBranches 214632552 # Number of Branches instructions committed system.cpu.comFloats 190 # Number of Floating Point instructions committed system.cpu.comInts 916086844 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 9111643 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4081.685602 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27335.708502 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 162429806 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.execution_unit.executions 1162207758 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 135407901 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 207004701 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 54777.453839 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 860 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.324416 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 664.403935 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324416 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 207004701 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54777.453839 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 2697152 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.458476 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.337280 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15023.339345 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11052.003329 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.458476 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.337280 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9112503 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52212.225711 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 26075.342674 # Cy system.cpu.l2cache.total_refs 7565242 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 230207194000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1170923 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.numCycles 1959902740 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 1801820745 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 1376202963 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 1456399909 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 902142172 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 895662206 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 923587455 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 422410393 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 932643705 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 902142172 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 895662206 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 923587455 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 422410393 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 932643705 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 1619523667 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 8517352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 2659460cd..73cbafb08 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 141143bd2..489ef9061 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:53 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:34 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 5851c27dd..bd83aa84a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172436 # Simulator instruction rate (inst/s) -host_mem_usage 208600 # Number of bytes of host memory used -host_seconds 10067.76 # Real time elapsed on the host -host_tick_rate 69724149 # Simulator tick rate (ticks/s) +host_inst_rate 279473 # Simulator instruction rate (inst/s) +host_mem_usage 204448 # Number of bytes of host memory used +host_seconds 6211.84 # Real time elapsed on the host +host_tick_rate 113004567 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.701966 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 19849428 # Nu system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 64109829 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1311318680 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.387748 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1311318680 # Number of insts commited each cycle -system.cpu.commit.COM:count 1819780126 # Number of instructions committed -system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.COM:loads 444595663 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 605324165 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle +system.cpu.commit.count 1819780126 # Number of instructions committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction @@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses 9161274 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997370 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency @@ -129,15 +129,15 @@ system.cpu.dcache.tagsinuse 4085.228479 # Cy system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 3077964 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 69300100 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 734 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 53326576 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2753583044 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 704925020 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 533426665 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 83930076 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1732 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3666895 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle +system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running +system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 776927298 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 761318004 # DTB hits @@ -217,8 +217,8 @@ system.cpu.icache.demand_mshr_misses 913 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.349808 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency @@ -241,21 +241,13 @@ system.cpu.icache.total_refs 346934350 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 278210520 # Number of branches executed -system.cpu.iew.EXEC:nop 128264130 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.613458 # Inst execution rate -system.cpu.iew.EXEC:refs 776927311 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 203625107 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1505740839 # num instructions consuming a value -system.cpu.iew.WB:count 2224607717 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.814091 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1225810379 # num instructions producing a value -system.cpu.iew.WB:rate 1.584554 # insts written-back per cycle -system.cpu.iew.WB:sent 2246216503 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 278210520 # Number of branches executed +system.cpu.iew.exec_nop 128264130 # number of nop insts executed +system.cpu.iew.exec_rate 1.613458 # Inst execution rate +system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed +system.cpu.iew.exec_stores 203625107 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions @@ -283,103 +275,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 66687540 # system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value +system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1225810379 # num instructions producing a value +system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle +system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2302863011 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12654324 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1395248756 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.650504 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1395248756 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.640295 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses @@ -391,6 +373,24 @@ system.cpu.iq.iqSquashedInstsExamined 686898644 # Nu system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle +system.cpu.iq.rate 1.640295 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -451,10 +451,10 @@ system.cpu.l2cache.demand_mshr_misses 2703837 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.482747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.327799 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency @@ -485,28 +485,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 1403932652 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 45015493 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2058465 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 721970868 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 493414 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3482054752 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2693944594 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2019690549 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 519735088 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 83930076 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 24596395 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 643487586 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 875387 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 3481179365 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 51588618 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 48 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running +system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3541690829 # The number of ROB reads system.cpu.rob.rob_writes 4844528665 # The number of ROB writes system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 56c0d3893..5e9a97c65 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:59:33 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 7812c0d15..c03fa7e28 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1468260 # Simulator instruction rate (inst/s) -host_mem_usage 218108 # Number of bytes of host memory used -host_seconds 1239.41 # Real time elapsed on the host -host_tick_rate 736791940 # Simulator tick rate (ticks/s) +host_inst_rate 6003103 # Simulator instruction rate (inst/s) +host_mem_usage 195756 # Number of bytes of host memory used +host_seconds 303.14 # Real time elapsed on the host +host_tick_rate 3012433327 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1376202618 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_mem_refs 611922547 # number of memory refs system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6d6374beb..6ccdf7868 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index b361f245f..6c70cf5a2 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:59:01 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index f893b334a..315c5ad86 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 590383 # Simulator instruction rate (inst/s) -host_mem_usage 225824 # Number of bytes of host memory used -host_seconds 3082.37 # Real time elapsed on the host -host_tick_rate 864089077 # Simulator tick rate (ticks/s) +host_inst_rate 2523486 # Simulator instruction rate (inst/s) +host_mem_usage 203508 # Number of bytes of host memory used +host_seconds 721.14 # Real time elapsed on the host +host_tick_rate 3693391340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9111734 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995973 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.299002 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 2697097 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.467301 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.327380 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1376202618 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_mem_refs 611922547 # number of memory refs system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5d9a2313d..2386e9fa4 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index cc554e99a..dc1adbfd8 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:48:59 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:21:07 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a38ba9b9e..5a7da6a72 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189685 # Simulator instruction rate (inst/s) -host_mem_usage 258720 # Number of bytes of host memory used -host_seconds 9083.85 # Real time elapsed on the host -host_tick_rate 70772893 # Simulator tick rate (ticks/s) +host_inst_rate 253143 # Simulator instruction rate (inst/s) +host_mem_usage 215164 # Number of bytes of host memory used +host_seconds 6806.72 # Real time elapsed on the host +host_tick_rate 94449374 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073854 # Number of instructions simulated sim_seconds 0.642891 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 18005065 # Nu system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 213462366 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 57604302 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1166659925 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.476929 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1166659925 # Number of insts commited each cycle -system.cpu.commit.COM:count 1723073872 # Number of instructions committed -system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1536941857 # Number of committed integer instructions. -system.cpu.commit.COM:loads 485926772 # Number of loads committed -system.cpu.commit.COM:membars 62 # Number of memory barriers committed -system.cpu.commit.COM:refs 660773819 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted +system.cpu.commit.branches 213462366 # Number of branches committed +system.cpu.commit.bw_lim_events 57604302 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1166659925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.476929 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1166659925 # Number of insts commited each cycle +system.cpu.commit.count 1723073872 # Number of instructions committed +system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.function_calls 13665177 # Number of function calls committed. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.membars 62 # Number of memory barriers committed +system.cpu.commit.refs 660773819 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1723073854 # Number of Instructions Simulated system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 9541290 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997826 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997826 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4087.096656 # Cy system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 3122149 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 127119222 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 630 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 46145837 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2344585205 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 578307676 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 449658106 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 70439042 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2261 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 11574920 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 127119222 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 630 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 46145837 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2344585205 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 578307676 # Number of cycles decode is idle +system.cpu.decode.RunCycles 449658106 # Number of cycles decode is running +system.cpu.decode.SquashCycles 70439042 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2261 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 11574920 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 713 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.281945 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.281945 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 276393684 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 233410057 # Number of branches executed -system.cpu.iew.EXEC:nop 371 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.517006 # Inst execution rate -system.cpu.iew.EXEC:refs 747857641 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 187754946 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2256424150 # num instructions consuming a value -system.cpu.iew.WB:count 1928710637 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.551017 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243327288 # num instructions producing a value -system.cpu.iew.WB:rate 1.500030 # insts written-back per cycle -system.cpu.iew.WB:sent 1934940770 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 233410057 # Number of branches executed +system.cpu.iew.exec_nop 371 # number of nop insts executed +system.cpu.iew.exec_rate 1.517006 # Inst execution rate +system.cpu.iew.exec_refs 747857641 # number of memory reference insts executed +system.cpu.iew.exec_stores 187754946 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 50405377 # system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2256424150 # num instructions consuming a value +system.cpu.iew.wb_count 1928710637 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.551017 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1243327288 # num instructions producing a value +system.cpu.iew.wb_rate 1.500030 # insts written-back per cycle +system.cpu.iew.wb_sent 1934940770 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1971666946 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 20875026 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1237098966 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593783 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1237098966 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.533439 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1971666946 # Type of FU issued system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 20875026 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 484979968 # Nu system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1237098966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.593783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1237098966 # Number of insts issued each cycle +system.cpu.iq.rate 1.533439 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses 2931748 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.487988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.329914 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487988 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.329914 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency @@ -495,28 +495,28 @@ system.cpu.misc_regfile_writes 128 # nu system.cpu.numCycles 1285781107 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 67172415 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1360917377 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14851346 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 600335413 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 10242 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6331353991 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2292668273 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1803116545 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 438383597 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 70439042 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 60752889 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 442199165 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 393 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6331353598 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 15610 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 650 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 118137729 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 645 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 67172415 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1360917377 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 14851346 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 600335413 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 10242 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 6331353991 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2292668273 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1803116545 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 438383597 # Number of cycles rename is running +system.cpu.rename.SquashCycles 70439042 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 60752889 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 442199165 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 393 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 6331353598 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 15610 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 650 # count of serializing insts renamed +system.cpu.rename.skidInsts 118137729 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 645 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3320275044 # The number of ROB reads system.cpu.rob.rob_writes 4492885352 # The number of ROB writes system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index b27b25e6d..8d90d74d0 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index d37b6d85d..4e09f0c47 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:50:12 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:22:49 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 0c882577d..bd13defc5 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1075067 # Simulator instruction rate (inst/s) -host_mem_usage 247128 # Number of bytes of host memory used -host_seconds 1602.76 # Real time elapsed on the host -host_tick_rate 537533999 # Simulator tick rate (ticks/s) +host_inst_rate 4004296 # Simulator instruction rate (inst/s) +host_mem_usage 206252 # Number of bytes of host memory used +host_seconds 430.31 # Real time elapsed on the host +host_tick_rate 2002150173 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073862 # Number of instructions simulated sim_seconds 0.861538 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 1329729952 # nu system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index b26c9b5f5..00bc540f8 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index 50181b6ce..88386aeb5 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:14:16 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:25:15 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index b09cdeb30..1dcb25e1c 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 536583 # Simulator instruction rate (inst/s) -host_mem_usage 254860 # Number of bytes of host memory used -host_seconds 3200.38 # Real time elapsed on the host -host_tick_rate 759728459 # Simulator tick rate (ticks/s) +host_inst_rate 2103726 # Simulator instruction rate (inst/s) +host_mem_usage 213996 # Number of bytes of host memory used +host_seconds 816.30 # Real time elapsed on the host +host_tick_rate 2978588238 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1717270343 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 9115236 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997002 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 638 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.251403 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 2699469 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.458607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.338956 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15027.621217 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11106.896016 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.458607 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.338956 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9115874 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 1329729952 # nu system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 403cb4d0b..fd345ce8f 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:22:46 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 9e70ccdd1..3863ba265 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2540540 # Simulator instruction rate (inst/s) -host_mem_usage 223860 # Number of bytes of host memory used -host_seconds 1844.83 # Real time elapsed on the host -host_tick_rate 1542694185 # Simulator tick rate (ticks/s) +host_inst_rate 2952357 # Simulator instruction rate (inst/s) +host_mem_usage 202444 # Number of bytes of host memory used +host_seconds 1587.50 # Real time elapsed on the host +host_tick_rate 1792761763 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 4679057393 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index a92ea4a1d..c75881c3f 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 65c0a8840..60300fa55 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:36:40 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 59534c87e..e9ae83f48 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1546064 # Simulator instruction rate (inst/s) -host_mem_usage 231584 # Number of bytes of host memory used -host_seconds 3031.48 # Real time elapsed on the host -host_tick_rate 1954011316 # Simulator tick rate (ticks/s) +host_inst_rate 1878760 # Simulator instruction rate (inst/s) +host_mem_usage 210192 # Number of bytes of host memory used +host_seconds 2494.66 # Real time elapsed on the host +host_tick_rate 2374493636 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9112677 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.271344 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 2717345 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.336564 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 4679057393 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- |