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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch) | |
| tree | 79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/long/60.bzip2/ref | |
| parent | 77853b9f529947c3a9db78ef3458289f387289ce (diff) | |
| download | gem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz | |
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/long/60.bzip2/ref')
| -rwxr-xr-x | tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 11 |
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 66c445ccc..b301ecfc9 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 08:53:40 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 04e1f7d7c..aaad6352f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144806 # Simulator instruction rate (inst/s) -host_mem_usage 206568 # Number of bytes of host memory used -host_seconds 11988.72 # Real time elapsed on the host -host_tick_rate 60389347 # Simulator tick rate (ticks/s) +host_inst_rate 148199 # Simulator instruction rate (inst/s) +host_mem_usage 206348 # Number of bytes of host memory used +host_seconds 11714.26 # Real time elapsed on the host +host_tick_rate 61804258 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.723991 # Number of seconds simulated @@ -153,9 +153,10 @@ system.cpu.dtb.write_hits 194797036 # DT system.cpu.dtb.write_misses 6192363 # DTB write misses system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched -system.cpu.fetch.Cycles 911372250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 556959890 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss |