diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
| commit | b5736ba4ef3ae82238c7c9811e182c8a13a58fdd (patch) | |
| tree | ce28586e5b2957d629b7041e78cc56cc7e1457ed /tests/long/60.bzip2/ref | |
| parent | affad299320e767b18c45a760c69a1ef287565bc (diff) | |
| download | gem5-b5736ba4ef3ae82238c7c9811e182c8a13a58fdd.tar.xz | |
alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
Diffstat (limited to 'tests/long/60.bzip2/ref')
9 files changed, 712 insertions, 739 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 4b8d5a543..96ed5aa20 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:06:19 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 07:58:23 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d22652a78..ebab377c0 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,170 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172416 # Simulator instruction rate (inst/s) -host_mem_usage 207720 # Number of bytes of host memory used -host_seconds 10068.91 # Real time elapsed on the host -host_tick_rate 69716202 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.701966 # Number of seconds simulated sim_ticks 701966325500 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle -system.cpu.commit.count 1819780126 # Number of instructions committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.loads 444595663 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency -system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses -system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 670151455 # number of overall hits -system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses -system.cpu.dcache.overall_misses 14741918 # number of overall misses -system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9157179 # number of replacements -system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use -system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3077964 # number of writebacks -system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle -system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running -system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 776927298 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 761318004 # DTB hits -system.cpu.dtb.data_misses 15609294 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 187255 # Simulator instruction rate (inst/s) +host_tick_rate 75716158 # Simulator tick rate (ticks/s) +host_mem_usage 193592 # Number of bytes of host memory used +host_seconds 9271.02 # Real time elapsed on the host +sim_insts 1736043781 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 573302197 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 563960671 # DTB read hits system.cpu.dtb.read_misses 9341526 # DTB read misses -system.cpu.dtb.write_accesses 203625101 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 573302197 # DTB read accesses system.cpu.dtb.write_hits 197357333 # DTB write hits system.cpu.dtb.write_misses 6267768 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 203625101 # DTB write accesses +system.cpu.dtb.data_hits 761318004 # DTB hits +system.cpu.dtb.data_misses 15609294 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 776927298 # DTB accesses +system.cpu.itb.fetch_hits 346935606 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 346935639 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 1403932652 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched +system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total) @@ -182,111 +78,98 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 788 # number of floating regfile reads -system.cpu.fp_regfile_writes 457 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency -system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 346934350 # number of overall hits -system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1256 # number of overall misses -system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use -system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 278210520 # Number of branches executed -system.cpu.iew.exec_nop 128264130 # number of nop insts executed -system.cpu.iew.exec_rate 1.613458 # Inst execution rate -system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed -system.cpu.iew.exec_stores 203625107 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value -system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1225810379 # num instructions producing a value -system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle -system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads -system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes -system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads +system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued @@ -322,191 +205,308 @@ system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued -system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes +system.cpu.iq.rate 1.640295 # Inst issue rate system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle -system.cpu.iq.rate 1.640295 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 346935639 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 346935606 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency +system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 128264130 # number of nop insts executed +system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed +system.cpu.iew.exec_branches 278210520 # Number of branches executed +system.cpu.iew.exec_stores 203625107 # Number of stores executed +system.cpu.iew.exec_rate 1.613458 # Inst execution rate +system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1225810379 # num instructions producing a value +system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle +system.cpu.commit.count 1819780126 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3541690829 # The number of ROB reads +system.cpu.rob.rob_writes 4844528665 # The number of ROB writes +system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated +system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads +system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads +system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes +system.cpu.fp_regfile_reads 788 # number of floating regfile reads +system.cpu.fp_regfile_writes 457 # number of floating regfile writes +system.cpu.misc_regfile_reads 25 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use +system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits +system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits +system.cpu.icache.overall_hits 346934350 # number of overall hits +system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses +system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1256 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9157179 # number of replacements +system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use +system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 670151455 # number of overall hits +system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 14741918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 3077964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2693244 # number of replacements +system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6458351 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits +system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2703837 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1171773 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6458351 # number of overall hits -system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2703837 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2693244 # number of replacements -system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1171773 # number of writebacks -system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 25 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 1403932652 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running -system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3541690829 # The number of ROB reads -system.cpu.rob.rob_writes 4844528665 # The number of ROB writes -system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 5e9a97c65..eccdc3c2f 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:59:33 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 20 2011 12:23:57 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index c03fa7e28..0df85f934 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6003103 # Simulator instruction rate (inst/s) -host_mem_usage 195756 # Number of bytes of host memory used -host_seconds 303.14 # Real time elapsed on the host -host_tick_rate 3012433327 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated sim_ticks 913189263000 # Number of ticks simulated -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3384825 # Simulator instruction rate (inst/s) +host_tick_rate 1698548817 # Simulator tick rate (ticks/s) +host_mem_usage 183944 # Number of bytes of host memory used +host_seconds 537.63 # Real time elapsed on the host +sim_insts 1819780127 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 444595663 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449492741 # DTB read accesses system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1826378527 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.data_hits 605324165 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 611922547 # DTB accesses system.cpu.itb.fetch_hits 1826378509 # ITB hits system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1826378527 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls system.cpu.numCycles 1826378527 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1826378527 # Number of busy cycles -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_fp_insts 805526 # number of float instructions system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1826378527 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 6c70cf5a2..1b40535c5 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:59:01 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 20 2011 12:54:26 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 315c5ad86..03eecacc7 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,255 +1,255 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2523486 # Simulator instruction rate (inst/s) -host_mem_usage 203508 # Number of bytes of host memory used -host_seconds 721.14 # Real time elapsed on the host -host_tick_rate 3693391340 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated sim_ticks 2663443716000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9111734 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3058802 # number of writebacks -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1486818 # Simulator instruction rate (inst/s) +host_tick_rate 2176118189 # Simulator tick rate (ticks/s) +host_mem_usage 192584 # Number of bytes of host memory used +host_seconds 1223.94 # Real time elapsed on the host +sim_insts 1819780127 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 444595663 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449492741 # DTB read accesses system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.data_hits 605324165 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 611922547 # DTB accesses +system.cpu.itb.fetch_hits 1826378510 # ITB hits +system.cpu.itb.fetch_misses 18 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1826378528 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 5326887432 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_store_insts 162429806 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5326887432 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use +system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits +system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1826377708 # number of overall hits +system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses +system.cpu.icache.demand_misses 802 # number of demand (read+write) misses +system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 802 # number of demand (read+write) misses +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 802 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1826378528 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1826378510 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9107638 # number of replacements +system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use +system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 3058802 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2686269 # number of replacements +system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6415439 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits +system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2697097 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1170923 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6415439 # number of overall hits -system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2697097 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2686269 # number of replacements -system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1170923 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5326887432 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 5326887432 # Number of busy cycles -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |