diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
| commit | 567cab685965e4e627ac1541a9fdacb93fd6e5fe (patch) | |
| tree | d79f8cfd677dfc314ccb48630b77785412a9f1bd /tests/long/60.bzip2/ref | |
| parent | ca3d82b38ab92114f5056a35bacf0dceb8b6d4a6 (diff) | |
| download | gem5-567cab685965e4e627ac1541a9fdacb93fd6e5fe.tar.xz | |
stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
Diffstat (limited to 'tests/long/60.bzip2/ref')
6 files changed, 167 insertions, 167 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index a3fed9503..d46e4c412 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:40 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:10:17 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index f9cc5dfc4..8a66d53b4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165473 # Simulator instruction rate (inst/s) -host_mem_usage 204148 # Number of bytes of host memory used -host_seconds 10491.39 # Real time elapsed on the host -host_tick_rate 70754150 # Simulator tick rate (ticks/s) +host_inst_rate 225916 # Simulator instruction rate (inst/s) +host_mem_usage 205860 # Number of bytes of host memory used +host_seconds 7684.48 # Real time elapsed on the host +host_tick_rate 96598522 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 23750300 # Nu system.cpu.commit.COM:branches 214632552 # Number of branches committed system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1379215339 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 736540831 5340.29% - 1 260049504 1885.49% - 2 126970462 920.60% - 3 77723426 563.53% - 4 51327439 372.15% - 5 27759546 201.27% - 6 26179568 189.81% - 7 9881978 71.65% - 8 62782585 455.21% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 1379215339 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 736540831 53.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 260049504 18.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 126970462 9.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 77723426 5.64% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 51327439 3.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 27759546 2.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 26179568 1.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 9881978 0.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 62782585 4.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1379215339 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.319431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.090314 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed system.cpu.commit.COM:loads 445666361 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -79,13 +81,13 @@ system.cpu.dcache.WriteReq_mshr_hits 3182477 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6337.465393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 31613.485382 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 156253 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 990247980 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2065309000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency @@ -104,7 +106,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 668251814 # number of overall hits system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses @@ -157,21 +159,23 @@ system.cpu.fetch.branchRate 0.232721 # Nu system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1472299541 -system.cpu.fetch.rateDist.min_value 0 - 0 907273323 6162.29% - 1 47886355 325.25% - 2 34613456 235.10% - 3 52095475 353.84% - 4 125971058 855.61% - 5 69335096 470.93% - 6 50458684 342.72% - 7 40993758 278.43% - 8 143672336 975.84% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 1472299541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 907273323 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 47886355 3.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 34613456 2.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 52095475 3.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 125971058 8.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 69335096 4.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 50458684 3.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 40993758 2.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 143672336 9.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1472299541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.944609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.837831 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency @@ -183,13 +187,13 @@ system.cpu.icache.ReadReq_mshr_hits 332 # nu system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency @@ -208,7 +212,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 355179284 # number of overall hits system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses @@ -271,58 +275,54 @@ system.cpu.iew.predictedNotTakenIncorrect 703796 # N system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1532920254 66.19% # Type of FU issued - IntMult 99 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 234 0.00% # Type of FU issued - FloatCmp 20 0.00% # Type of FU issued - FloatCvt 143 0.00% # Type of FU issued - FloatMult 16 0.00% # Type of FU issued - FloatDiv 24 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 577889733 24.95% # Type of FU issued - MemWrite 205034377 8.85% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920254 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 99 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 143 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 577889733 24.95% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 205034377 8.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 2315844900 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2738956 19.03% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9224843 64.09% # attempts to use FU when none available - MemWrite 2429770 16.88% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% -system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2738956 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 9224843 64.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 2429770 16.88% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued @@ -377,13 +377,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11899.405570 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 39818 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 473810531 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency @@ -402,7 +402,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5387454 # number of overall hits system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 3314840b7..154e8b6b0 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:41:08 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:13:47 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 5f4f3edad..106a8a8a6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1697488 # Simulator instruction rate (inst/s) -host_mem_usage 203260 # Number of bytes of host memory used -host_seconds 1072.04 # Real time elapsed on the host -host_tick_rate 2544665146 # Simulator tick rate (ticks/s) +host_inst_rate 2540644 # Simulator instruction rate (inst/s) +host_mem_usage 204972 # Number of bytes of host memory used +host_seconds 716.27 # Real time elapsed on the host +host_tick_rate 3808619272 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 2247802 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 802 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1826377708 # number of overall hits system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5348043 # number of overall hits system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index aa3bb16f1..b190e5ac3 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:50:36 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:42:41 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index f81f1eda7..103b5bcb4 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1080301 # Simulator instruction rate (inst/s) -host_mem_usage 205584 # Number of bytes of host memory used -host_seconds 4307.30 # Real time elapsed on the host -host_tick_rate 1390213645 # Simulator tick rate (ticks/s) +host_inst_rate 1577505 # Simulator instruction rate (inst/s) +host_mem_usage 207544 # Number of bytes of host memory used +host_seconds 2949.71 # Real time elapsed on the host +host_tick_rate 2030054219 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176270 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 2247102 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1668242528 # number of overall hits system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 675 # nu system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 5945529.207407 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4013232890 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4013232215 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5328546 # number of overall hits system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses |