Update statistics for the last three revisions

--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24

2 files changed, 12 insertions, 12 deletions

diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
index 57430d61b..752f725e4 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect               19407214                       # Nu
 global.BPredUnit.condPredicted              254124044                       # Number of conditional branches predicted
 global.BPredUnit.lookups                    329654644                       # Number of BP lookups
 global.BPredUnit.usedRAS                     23321143                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 153530                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182552                       # Number of bytes of host memory used
-host_seconds                                 11307.49                       # Real time elapsed on the host
-host_tick_rate                               57851122                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 162413                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200732                       # Number of bytes of host memory used
+host_seconds                                 10689.07                       # Real time elapsed on the host
+host_tick_rate                               61198134                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           71970991                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          36581423                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             594992654                       # Number of loads inserted to the mem dependence unit.
@@ -244,10 +244,10 @@ system.cpu.icache.tagsinuse                710.981871                       # Cy
 system.cpu.icache.total_refs                338458990                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          287621                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             197                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                270496646                       # Number of branches executed
 system.cpu.iew.EXEC:nop                     123104849                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.690527                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.690526                       # Inst execution rate
 system.cpu.iew.EXEC:refs                    759555990                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                  199980185                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -436,7 +436,7 @@ system.cpu.l2cache.tagsinuse             18802.772660                       # Cy
 system.cpu.l2cache.total_refs                 5868601                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          505903232000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                       1308302031                       # number of cpu cycles simulated
+system.cpu.numCycles                       1308302228                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          9337867                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         3445352                       # Number of times rename has blocked due to IQ full
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
index a6eb50453..afbd9c385 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1514723                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181532                       # Number of bytes of host memory used
-host_seconds                                  1201.39                       # Real time elapsed on the host
-host_tick_rate                             2161875158                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1279505                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199716                       # Number of bytes of host memory used
+host_seconds                                  1422.25                       # Real time elapsed on the host
+host_tick_rate                             1826162604                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.597265                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                 5824390                       # To
 system.cpu.l2cache.warmup_cycle          2034930554000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2597265186000                       # number of cpu cycles simulated
+system.cpu.numCycles                       5194530372                       # number of cpu cycles simulated
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
 system.cpu.num_refs                         613169725                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls