diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/60.bzip2 | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/long/60.bzip2')
27 files changed, 311 insertions, 91 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 5e62dfe3a..28a997af9 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index b301ecfc9..d5dabed4c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:24:57 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index aaad6352f..025b36e9a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 148199 # Simulator instruction rate (inst/s) -host_mem_usage 206348 # Number of bytes of host memory used -host_seconds 11714.26 # Real time elapsed on the host -host_tick_rate 61804258 # Simulator tick rate (ticks/s) +host_inst_rate 163492 # Simulator instruction rate (inst/s) +host_mem_usage 226772 # Number of bytes of host memory used +host_seconds 10618.50 # Real time elapsed on the host +host_tick_rate 68182084 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.723991 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1347786892 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed +system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.COM:loads 444595663 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 605324165 # Number of memory references committed @@ -179,6 +182,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1436774330 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 752 # number of floating regfile reads +system.cpu.fp_regfile_writes 445 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 354412327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35305.051302 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717 # average ReadReq mshr miss latency @@ -278,6 +283,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 71840083 # system.cpu.iew.memOrderViolationEvents 2851639 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3390000 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18332236 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3052206207 # number of integer regfile reads +system.cpu.int_regfile_writes 1779704780 # number of integer regfile writes system.cpu.ipc 1.198940 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.198940 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -369,6 +376,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1436774330 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.592073 # Inst issue rate +system.cpu.iq.fp_alu_accesses 831640 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 1663270 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 822278 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 878238 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2317801511 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 6060328576 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2227662406 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3193875126 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2474285485 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2305294087 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ @@ -465,7 +480,11 @@ system.cpu.memDep0.conflictingLoads 123159990 # Nu system.cpu.memDep0.conflictingStores 64312407 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 617102957 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 232568585 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 25 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 1447982395 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 51393371 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 5887635 # Number of times rename has blocked due to IQ full @@ -479,10 +498,14 @@ system.cpu.rename.RENAME:RunCycles 528076479 # Nu system.cpu.rename.RENAME:SquashCycles 88987438 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 27475071 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 671478700 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 885045 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 3534388873 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 54007891 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3612840225 # The number of ROB reads +system.cpu.rob.rob_writes 4916793262 # The number of ROB writes system.cpu.timesIdled 425188 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 889a2c50f..e886c5917 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 5c31e9414..56c0d3893 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:35:16 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 0e81a5825..7812c0d15 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5747960 # Simulator instruction rate (inst/s) -host_mem_usage 231948 # Number of bytes of host memory used -host_seconds 316.60 # Real time elapsed on the host -host_tick_rate 2884399053 # Simulator tick rate (ticks/s) +host_inst_rate 1468260 # Simulator instruction rate (inst/s) +host_mem_usage 218108 # Number of bytes of host memory used +host_seconds 1239.41 # Real time elapsed on the host +host_tick_rate 736791940 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1826378527 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1826378527 # Number of busy cycles +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 611922547 # Number of memory references +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6c6b88ddd..6d6374beb 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index d211942d5..b361f245f 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:53:28 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 7c181b6aa..f893b334a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2423488 # Simulator instruction rate (inst/s) -host_mem_usage 239668 # Number of bytes of host memory used -host_seconds 750.89 # Real time elapsed on the host -host_tick_rate 3547033530 # Simulator tick rate (ticks/s) +host_inst_rate 590383 # Simulator instruction rate (inst/s) +host_mem_usage 225824 # Number of bytes of host memory used +host_seconds 3082.37 # Real time elapsed on the host +host_tick_rate 864089077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 582065656000 # Cy system.cpu.l2cache.writebacks 1170923 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5326887432 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5326887432 # Number of busy cycles +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 611922547 # Number of memory references +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 3ef4a25fb..731b0df43 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 2f2c51bdb..e9bf20924 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:57:47 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ab126a693..24c1e17c3 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165173 # Simulator instruction rate (inst/s) -host_mem_usage 251872 # Number of bytes of host memory used -host_seconds 10349.18 # Real time elapsed on the host -host_tick_rate 71148819 # Simulator tick rate (ticks/s) +host_inst_rate 152870 # Simulator instruction rate (inst/s) +host_mem_usage 238404 # Number of bytes of host memory used +host_seconds 11182.08 # Real time elapsed on the host +host_tick_rate 65849295 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.736332 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle system.cpu.commit.COM:count 1709408682 # Number of instructions committed +system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1523276792 # Number of committed integer instructions. system.cpu.commit.COM:loads 485926830 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 660773875 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 66 # number of floating regfile reads +system.cpu.fp_regfile_writes 62 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 145359637 # system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5217275964 # number of integer regfile reads +system.cpu.int_regfile_writes 1582136898 # number of integer regfile writes system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 78 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2136057911 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5702380947 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2009251443 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3154359191 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 102861524 # Nu system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3121183601 # number of misc regfile reads +system.cpu.misc_regfile_writes 895 # number of misc regfile writes system.cpu.numCycles 1472664444 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full @@ -477,10 +496,14 @@ system.cpu.rename.RENAME:RunCycles 526018927 # Nu system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1008 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 7136668460 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3717337450 # The number of ROB reads +system.cpu.rob.rob_writes 4979785274 # The number of ROB writes system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 14dc84cb3..8d90d74d0 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index 9eea795e5..1ce869a83 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:23 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 11106ff07..8d3a8d25e 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2718053 # Simulator instruction rate (inst/s) -host_mem_usage 254288 # Number of bytes of host memory used -host_seconds 628.91 # Real time elapsed on the host -host_tick_rate 1359028059 # Simulator tick rate (ticks/s) +host_inst_rate 1030645 # Simulator instruction rate (inst/s) +host_mem_usage 229520 # Number of bytes of host memory used +host_seconds 1658.58 # Real time elapsed on the host +host_tick_rate 515323054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.854706 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1709411231 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1709411231 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1709408682 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 4636623941 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065665 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index d8eed8875..3f9e59a85 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr index eabe42249..cdafa164c 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index fd7ecdb8c..ba8cd6dca 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:48:19 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 4a18c77a9..923e9c734 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 640383 # Simulator instruction rate (inst/s) -host_mem_usage 262008 # Number of bytes of host memory used -host_seconds 2660.29 # Real time elapsed on the host -host_tick_rate 913967481 # Simulator tick rate (ticks/s) +host_inst_rate 495941 # Simulator instruction rate (inst/s) +host_mem_usage 237232 # Number of bytes of host memory used +host_seconds 3435.10 # Real time elapsed on the host +host_tick_rate 707817123 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1703605163 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 538044067000 # Cy system.cpu.l2cache.writebacks 1171981 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4862840230 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4862840230 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1703605163 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 5115465619 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065727 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 56d944c30..89aae9c00 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 2a66d5524..228e6ab0c 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 90a5205b5..a0361e843 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1732973 # Simulator instruction rate (inst/s) -host_mem_usage 219700 # Number of bytes of host memory used -host_seconds 2704.52 # Real time elapsed on the host -host_tick_rate 1052314398 # Simulator tick rate (ticks/s) +host_inst_rate 1421831 # Simulator instruction rate (inst/s) +host_mem_usage 223380 # Number of bytes of host memory used +host_seconds 3296.36 # Real time elapsed on the host +host_tick_rate 863379215 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 2846007259500 # N system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5692014520 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5692014520 # Number of busy cycles +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_refs 1677713086 # Number of memory references +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index c92e9f8b5..a92ea4a1d 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index ecac67c27..2ae184132 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index c70e9b64d..21d2dce98 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 845010 # Simulator instruction rate (inst/s) -host_mem_usage 227416 # Number of bytes of host memory used -host_seconds 5546.52 # Real time elapsed on the host -host_tick_rate 1067976230 # Simulator tick rate (ticks/s) +host_inst_rate 980837 # Simulator instruction rate (inst/s) +host_mem_usage 231100 # Number of bytes of host memory used +host_seconds 4778.43 # Real time elapsed on the host +host_tick_rate 1239642391 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 1324806325000 # C system.cpu.l2cache.writebacks 1174631 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11847096156 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 11847096156 # Number of busy cycles +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_refs 1677713086 # Number of memory references +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- |