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authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:27:53 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:27:53 -0700
commita51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch)
tree8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/60.bzip2
parente7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff)
downloadgem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz
Stats: Update the stats.
--HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/60.bzip2')
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini82
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt607
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini18
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt36
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini12
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt62
6 files changed, 467 insertions, 350 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 105e8c6e2..e0dba3f8d 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -35,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
+dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -52,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2
issueToExecuteDelay=1
issueWidth=8
+itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
@@ -74,8 +77,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@@ -85,21 +98,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -107,12 +120,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -121,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@@ -128,11 +143,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@@ -206,11 +221,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@@ -218,11 +233,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@@ -248,11 +263,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -260,21 +275,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -282,12 +297,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -296,23 +309,27 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -320,12 +337,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -343,6 +358,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
@@ -366,7 +384,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
index dccb62bee..57430d61b 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 236329759 # Number of BTB hits
-global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted
-global.BPredUnit.lookups 265702680 # Number of BP lookups
-global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target.
-host_inst_rate 104740 # Simulator instruction rate (inst/s)
-host_mem_usage 154596 # Number of bytes of host memory used
-host_seconds 16574.74 # Real time elapsed on the host
-host_tick_rate 38540500 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 295839321 # Number of BTB hits
+global.BPredUnit.BTBLookups 304173613 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 120 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 19407214 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 254124044 # Number of conditional branches predicted
+global.BPredUnit.lookups 329654644 # Number of BP lookups
+global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target.
+host_inst_rate 153530 # Simulator instruction rate (inst/s)
+host_mem_usage 182552 # Number of bytes of host memory used
+host_seconds 11307.49 # Real time elapsed on the host
+host_tick_rate 57851122 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 71970991 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 36581423 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 594992654 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 221743675 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
-sim_seconds 0.638799 # Number of seconds simulated
-sim_ticks 638798750000 # Number of ticks simulated
+sim_seconds 0.654151 # Number of seconds simulated
+sim_ticks 654151113500 # Number of ticks simulated
system.cpu.commit.COM:branches 214632552 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 63247574 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 1240430038
+system.cpu.commit.COM:committed_per_cycle.samples 1235798441
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 616961832 4973.77%
- 1 236071207 1903.14%
- 2 130159070 1049.31%
- 3 77572840 625.37%
- 4 40072787 323.06%
- 5 42334502 341.29%
- 6 22413470 180.69%
- 7 14526859 117.11%
- 8 60317471 486.26%
+ 0 591538606 4786.69%
+ 1 262725137 2125.95%
+ 2 125553765 1015.97%
+ 3 79229995 641.12%
+ 4 49991526 404.53%
+ 5 29482834 238.57%
+ 6 23306420 188.59%
+ 7 10722584 86.77%
+ 8 63247574 511.80%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,70 +43,80 @@ system.cpu.commit.COM:loads 445666361 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 19406708 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 476380119 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked
+system.cpu.cpi 0.753611 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.753611 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 7500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 5500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 7500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 5500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 511433561 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 6211.231687 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.921493 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 504159044 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 45183710500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.014224 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7274517 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 1442446 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 23576138500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.014224 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7274517 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 158840549 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 13691.838043 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7367.789283 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 156591934 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 30787672401 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.014156 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2248615 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1887953 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 16567321498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.014156 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2248615 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 1521.266534 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 1667.900476 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 72.179758 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 34791 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 65110 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 52926384 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 108597000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 670274110 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 7977.562728 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 660750978 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 75971382901 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.014208 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9523132 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 3330399 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 40143459998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.014208 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9523132 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 670274110 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 7977.562728 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 609102856 # number of overall hits
-system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 11929003 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 660750978 # number of overall hits
+system.cpu.dcache.overall_miss_latency 75971382901 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.014208 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9523132 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 3330399 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 40143459998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.014208 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9523132 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9171759 # number of replacements
-system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9155187 # number of replacements
+system.cpu.dcache.sampled_refs 9159283 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use
-system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2245633 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched
-system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4084.725965 # Cycle average of tags in use
+system.cpu.dcache.total_refs 661114830 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 6949550000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2245528 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 23691683 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 575 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 51434078 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2685033161 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 684622025 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 525046007 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 72503589 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1687 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 2438727 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 758263361 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 743549453 # DTB hits
+system.cpu.dtb.misses 14713908 # DTB misses
+system.cpu.dtb.read_accesses 558500359 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 549711515 # DTB read hits
+system.cpu.dtb.read_misses 8788844 # DTB read misses
+system.cpu.dtb.write_accesses 199763002 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 193837938 # DTB write hits
+system.cpu.dtb.write_misses 5925064 # DTB write misses
+system.cpu.fetch.Branches 329654644 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 338459974 # Number of cache lines fetched
+system.cpu.fetch.Cycles 875922763 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 8905677 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2732615549 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 26330328 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.251971 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 338459974 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 319160464 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.088673 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 1277597526
+system.cpu.fetch.rateDist.samples 1308302031
system.cpu.fetch.rateDist.min_value 0
- 0 882806946 6909.90%
- 1 27356477 214.12%
- 2 16416749 128.50%
- 3 27123610 212.30%
- 4 80197027 627.72%
- 5 46838848 366.62%
- 6 25144427 196.81%
- 7 24073126 188.42%
- 8 147640316 1155.61%
+ 0 770839278 5891.91%
+ 1 46037022 351.88%
+ 2 31884256 243.71%
+ 3 48862894 373.48%
+ 4 119031598 909.82%
+ 5 67260927 514.11%
+ 6 45605029 348.58%
+ 7 40088084 306.41%
+ 8 138692943 1060.10%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 338459894 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7804.756637 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5448.008850 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 338458990 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 7055500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 904 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4925000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 904 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 374401.537611 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
-system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 338459894 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 7804.756637 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency
+system.cpu.icache.demand_hits 338458990 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 947 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 904 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4925000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 904 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 338459894 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 7804.756637 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 277956896 # number of overall hits
-system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles
+system.cpu.icache.overall_hits 338458990 # number of overall hits
+system.cpu.icache.overall_miss_latency 7055500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 947 # number of overall misses
-system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 904 # number of overall misses
+system.cpu.icache.overall_mshr_hits 80 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4925000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 904 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -216,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 904 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use
-system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 710.981871 # Cycle average of tags in use
+system.cpu.icache.total_refs 338458990 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 231142223 # Number of branches executed
-system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate
-system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 168419462 # Number of stores executed
+system.cpu.idleCycles 287621 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 270496646 # Number of branches executed
+system.cpu.iew.EXEC:nop 123104849 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.690527 # Inst execution rate
+system.cpu.iew.EXEC:refs 759555990 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 199980185 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value
-system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1477074275 # num instructions consuming a value
+system.cpu.iew.WB:count 2172910283 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.814315 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 991749121 # num instructions producing a value
-system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle
-system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1202803999 # num instructions producing a value
+system.cpu.iew.WB:rate 1.660863 # insts written-back per cycle
+system.cpu.iew.WB:sent 2193655848 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21011443 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 889547 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 594992654 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 23236593 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 221743675 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2499789620 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 559575805 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 40783059 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2211719338 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 12131 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 5627 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 72503589 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 62383 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 123404 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 36795200 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 338162 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 340968 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 149326293 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 60838693 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 340968 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 705259 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 20306184 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.326944 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.326944 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2252502397 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 1224165146 65.09% # Type of FU issued
- IntMult 78 0.00% # Type of FU issued
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 1478322730 65.63% # Type of FU issued
+ IntMult 88 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 199 0.00% # Type of FU issued
- FloatCmp 15 0.00% # Type of FU issued
- FloatCvt 141 0.00% # Type of FU issued
- FloatMult 13 0.00% # Type of FU issued
+ FloatAdd 219 0.00% # Type of FU issued
+ FloatCmp 16 0.00% # Type of FU issued
+ FloatCvt 143 0.00% # Type of FU issued
+ FloatMult 14 0.00% # Type of FU issued
FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 487297898 25.91% # Type of FU issued
- MemWrite 169129941 8.99% # Type of FU issued
+ MemRead 570745758 25.34% # Type of FU issued
+ MemWrite 203433405 9.03% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 16701897 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.007415 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 753308 5.08% # attempts to use FU when none available
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 2428134 14.54% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -297,84 +319,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 10126775 68.23% # attempts to use FU when none available
- MemWrite 3961138 26.69% # attempts to use FU when none available
+ MemRead 10594349 63.43% # attempts to use FU when none available
+ MemWrite 3679414 22.03% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526
+system.cpu.iq.ISSUE:issued_per_cycle.samples 1308302031
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 550473495 4308.66%
- 1 242915598 1901.35%
- 2 174612702 1366.73%
- 3 111937959 876.16%
- 4 91216702 713.97%
- 5 63235343 494.96%
- 6 32411117 253.69%
- 7 9228529 72.23%
- 8 1566081 12.26%
+ 0 464994121 3554.18%
+ 1 246274545 1882.40%
+ 2 221057021 1689.65%
+ 3 136661440 1044.57%
+ 4 111222535 850.13%
+ 5 73372650 560.82%
+ 6 42938124 328.20%
+ 7 9505404 72.65%
+ 8 2276191 17.40%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate
-system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses
+system.cpu.iq.ISSUE:rate 1.721699 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2376684729 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2252502397 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 628382514 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 968135 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 253289566 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 338460010 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 338459974 # ITB hits
+system.cpu.itb.misses 36 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1884766 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 5021.667411 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3021.667411 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 9464668000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1884766 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5695136000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1884766 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7275421 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4312.514661 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2312.514661 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5169531 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 9081681500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.289453 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2105890 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4869901500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289453 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2105890 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 363856 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4839.580768 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2839.786894 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1760910500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 363856 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1033273500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 363856 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2245528 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 2245528 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 2245528 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.195595 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9160187 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4647.443804 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5169531 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 18546349500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.435652 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3990656 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10565037500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.435652 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3990656 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 9160187 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4647.443804 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 9224685 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2197691 # number of overall misses
+system.cpu.l2cache.overall_hits 5169531 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 18546349500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.435652 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3990656 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10565037500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.435652 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3990656 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -386,32 +429,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2135792 # number of replacements
-system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 1375756 # number of replacements
+system.cpu.l2cache.sampled_refs 1398753 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1039396 # number of writebacks
-system.cpu.numCycles 1277597526 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking
+system.cpu.l2cache.tagsinuse 18802.772660 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5868601 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 505903232000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 1308302031 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 9337867 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed
-system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 3445352 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 700444810 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 8719596 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 7541 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 3393542048 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2622643652 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1968531188 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 511623131 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 72503589 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 14392125 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 592328225 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 29038158 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
+system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index ab96f2ec5..378e34da6 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
-children=workload
+children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
+dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -25,11 +27,23 @@ phase=0
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
@@ -53,7 +67,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
index 4bc7b8152..ac280ef36 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 918892 # Simulator instruction rate (inst/s)
-host_mem_usage 148632 # Number of bytes of host memory used
-host_seconds 1980.41 # Real time elapsed on the host
-host_tick_rate 459446111 # Simulator tick rate (ticks/s)
+host_inst_rate 2729023 # Simulator instruction rate (inst/s)
+host_mem_usage 174164 # Number of bytes of host memory used
+host_seconds 666.82 # Real time elapsed on the host
+host_tick_rate 1369458693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780129 # Number of instructions simulated
-sim_seconds 0.909890 # Number of seconds simulated
-sim_ticks 909890064000 # Number of ticks simulated
+sim_insts 1819780127 # Number of instructions simulated
+sim_seconds 0.913189 # Number of seconds simulated
+sim_ticks 913189263000 # Number of ticks simulated
+system.cpu.dtb.accesses 611922547 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 605324165 # DTB hits
+system.cpu.dtb.misses 6598382 # DTB misses
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 1826378527 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 1826378509 # ITB hits
+system.cpu.itb.misses 18 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1819780129 # number of cpu cycles simulated
-system.cpu.num_insts 1819780129 # Number of instructions executed
-system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.numCycles 1826378527 # number of cpu cycles simulated
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index ef8186c31..9095d9dfe 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
+dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
@@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
[system.cpu.l2cache]
type=BaseCache
addr_range=0:18446744073709551615
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
index 6f7531c90..a6eb50453 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1593285 # Simulator instruction rate (inst/s)
-host_mem_usage 199472 # Number of bytes of host memory used
-host_seconds 1142.16 # Real time elapsed on the host
-host_tick_rate 2268225007 # Simulator tick rate (ticks/s)
+host_inst_rate 1514723 # Simulator instruction rate (inst/s)
+host_mem_usage 181532 # Number of bytes of host memory used
+host_seconds 1201.39 # Real time elapsed on the host
+host_tick_rate 2161875158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780129 # Number of instructions simulated
-sim_seconds 2.590667 # Number of seconds simulated
-sim_ticks 2590666806000 # Number of ticks simulated
+sim_insts 1819780127 # Number of instructions simulated
+sim_seconds 2.597265 # Number of seconds simulated
+sim_ticks 2597265186000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency
@@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.283777 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4079.325443 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40727264000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 40727877000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb.accesses 611922547 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 605324165 # DTB hits
+system.cpu.dtb.misses 6598382 # DTB misses
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
@@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
@@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 802 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1819779328 # number of overall hits
+system.cpu.icache.overall_hits 1826377708 # number of overall hits
system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses
@@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 611.417495 # Cycle average of tags in use
-system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 611.506832 # Cycle average of tags in use
+system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 1826378528 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 1826378510 # ITB hits
+system.cpu.itb.misses 18 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1367767 # number of replacements
system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18546.386002 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18552.565433 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2030116907000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2590666806000 # number of cpu cycles simulated
-system.cpu.num_insts 1819780129 # Number of instructions executed
-system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.numCycles 2597265186000 # number of cpu cycles simulated
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------