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authorAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
commitd114e5fae6ffb83a1145208532def7654cc9dd75 (patch)
treed54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/60.bzip2
parent02353a60ee6ce831302067aae38bc31b739f14e5 (diff)
downloadgem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz
Regression: Update stats for cache changes.
--HG-- extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/60.bzip2')
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini38
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt205
2 files changed, 129 insertions, 114 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 41806d538..ef8186c31 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
@@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
index 009ee213d..6f7531c90 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 637714 # Simulator instruction rate (inst/s)
-host_mem_usage 154060 # Number of bytes of host memory used
-host_seconds 2853.60 # Real time elapsed on the host
-host_tick_rate 886477792 # Simulator tick rate (ticks/s)
+host_inst_rate 1593285 # Simulator instruction rate (inst/s)
+host_mem_usage 199472 # Number of bytes of host memory used
+host_seconds 1142.16 # Real time elapsed on the host
+host_tick_rate 2268225007 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated
-sim_seconds 2.529655 # Number of seconds simulated
-sim_ticks 2529654621000 # Number of ticks simulated
+sim_seconds 2.590667 # Number of seconds simulated
+sim_ticks 2590666806000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 118818430000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 104373602000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 56195050000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 51699446000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 18480.410584 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 175013480000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 156073048000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 18480.410584 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 596212431 # number of overall hits
-system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.overall_hits 595853949 # number of overall hits
+system.cpu.dcache.overall_miss_latency 175013480000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9470216 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 156073048000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4079.283777 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 40727264000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks
system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 18446000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 18446000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1819779328 # number of overall hits
-system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 18446000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 611.417495 # Cycle average of tags in use
system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 41565040000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5145160 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 45717232000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.287691 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2078056 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 22858616000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287691 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2078056 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.018082 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 7886252000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2215611 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.012962 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 29097 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.012962 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 29097 # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 2244708 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 2244708 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.187898 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5145160 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 87282272000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.435376 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3967376 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 43641136000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.435376 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3967376 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 9167994 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2189250 # number of overall misses
+system.cpu.l2cache.overall_hits 5145160 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 87282272000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.435376 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3967376 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 43641136000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.435376 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3967376 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2127385 # number of replacements
-system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 1367767 # number of replacements
+system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1038202 # number of writebacks
+system.cpu.l2cache.tagsinuse 18546.386002 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2030116907000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2529654621000 # number of cpu cycles simulated
+system.cpu.numCycles 2590666806000 # number of cpu cycles simulated
system.cpu.num_insts 1819780129 # Number of instructions executed
system.cpu.num_refs 606571345 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls