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author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
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committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr | |
parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr')
-rwxr-xr-x | tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr index a263a334f..10a04a681 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr @@ -4,3 +4,6 @@ warn: Prefetching currently unimplemented For more information see: http://www.m5sim.org/warn/8028fa22 warn: Write Hints currently unimplemented For more information see: http://www.m5sim.org/warn/cfb3293b +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here |