diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | |
parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt')
-rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 256 |
1 files changed, 124 insertions, 132 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 4e98786e0..3c9f3dbf4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 33745 # Simulator instruction rate (inst/s) -host_mem_usage 211108 # Number of bytes of host memory used -host_seconds 2723.45 # Real time elapsed on the host -host_tick_rate 36107563 # Simulator tick rate (ticks/s) +host_inst_rate 54763 # Simulator instruction rate (inst/s) +host_mem_usage 197304 # Number of bytes of host memory used +host_seconds 1678.20 # Real time elapsed on the host +host_tick_rate 58595727 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098337 # Number of seconds simulated -sim_ticks 98337080000 # Number of ticks simulated +sim_seconds 0.098335 # Number of seconds simulated +sim_ticks 98335161000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064 system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 185972268 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 95.460360 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 95.462227 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43625545 # Number of Integer instructions committed @@ -42,28 +42,28 @@ system.cpu.comStores 6502695 # Nu system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads +system.cpu.cpi 2.139976 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.139976 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48524.210526 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23049000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55595.537757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52592.105263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 97181000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 91931000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54730.994152 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 121667000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114980000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352016 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.857733 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54730.994152 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495062 # number of overall hits -system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles +system.cpu.dcache.overall_hits 26495078 # number of overall hits +system.cpu.dcache.overall_miss_latency 121667000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2239 # number of overall misses +system.cpu.dcache.overall_misses 2223 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114980000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.857733 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.dcache.writebacks 107 # number of writebacks system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 26497301 # DTB hits @@ -126,50 +126,50 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_avg_miss_latency 27216.197508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.134662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 101754083 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 235910000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205719500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 8668 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205720500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8577 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2000 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11863.598578 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 11863.598344 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency -system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_avg_miss_latency 27216.197508 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency +system.cpu.icache.demand_hits 101754083 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 235910000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205719500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 8668 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205720500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8577 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.697636 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.759296 # Average occupied blocks per context system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 27216.197508 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 101754085 # number of overall hits -system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles +system.cpu.icache.overall_hits 101754083 # number of overall hits +system.cpu.icache.overall_miss_latency 235910000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8666 # number of overall misses -system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205719500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 8668 # number of overall misses +system.cpu.icache.overall_mshr_hits 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205720500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8577 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6743 # number of replacements system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use -system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.759296 # Cycle average of tags in use +system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads +system.cpu.idleCycles 8924453 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,104 +201,96 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.318235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.807201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89916500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68890000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52167.972576 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 159790500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.916906 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 52185.370951 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6015 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 249707000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443056 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4785 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 191471500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4785 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.063286 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2073.767582 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.791341 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52185.370951 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5989 # number of overall hits -system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4811 # number of overall misses +system.cpu.l2cache.overall_hits 6015 # number of overall hits +system.cpu.l2cache.overall_miss_latency 249707000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.443056 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4785 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 191471500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.443056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4785 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3129 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2091.558923 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5998 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 196674161 # number of cpu cycles simulated -system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed. +system.cpu.numCycles 196670323 # number of cpu cycles simulated +system.cpu.runCycles 187745870 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94907524 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 51.742834 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 104509809 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 46.860407 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 170133192 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.493206 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 196670323 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- |