summaryrefslogtreecommitdiff
path: root/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:27:53 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:27:53 -0700
commita51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch)
tree8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
parente7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff)
downloadgem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz
Stats: Update the stats.
--HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt')
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt34
1 files changed, 25 insertions, 9 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
index acfa7c9dd..127e45547 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 935813 # Simulator instruction rate (inst/s)
-host_mem_usage 150648 # Number of bytes of host memory used
-host_seconds 98.21 # Real time elapsed on the host
-host_tick_rate 467904361 # Simulator tick rate (ticks/s)
+host_inst_rate 2451408 # Simulator instruction rate (inst/s)
+host_mem_usage 179100 # Number of bytes of host memory used
+host_seconds 37.49 # Real time elapsed on the host
+host_tick_rate 1225693454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903057 # Number of instructions simulated
+sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated
-sim_ticks 45951528000 # Number of ticks simulated
+sim_ticks 45951567500 # Number of ticks simulated
+system.cpu.dtb.accesses 26497334 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 26497301 # DTB hits
+system.cpu.dtb.misses 33 # DTB misses
+system.cpu.dtb.read_accesses 19996208 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 19996198 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.write_accesses 6501126 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 6501103 # DTB write hits
+system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 91903136 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 91903089 # ITB hits
+system.cpu.itb.misses 47 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 91903057 # number of cpu cycles simulated
-system.cpu.num_insts 91903057 # Number of instructions executed
-system.cpu.num_refs 26537109 # Number of memory references
+system.cpu.numCycles 91903136 # number of cpu cycles simulated
+system.cpu.num_insts 91903056 # Number of instructions executed
+system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------