This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.

1 files changed, 56 insertions, 56 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index e6e809818..3b3e2ccb7 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,23 +1,23 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1922347                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206016                       # Number of bytes of host memory used
-host_seconds                                    47.81                       # Real time elapsed on the host
-host_tick_rate                             2483835101                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1637033                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206044                       # Number of bytes of host memory used
+host_seconds                                    56.14                       # Real time elapsed on the host
+host_tick_rate                             2115189911                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118747                       # Number of seconds simulated
-sim_ticks                                118747191000                       # Number of ticks simulated
+sim_ticks                                118747246000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               19995724                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       24318000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               19995723                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       24374000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  474                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     22896000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                  475                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     22949000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             474                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
@@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.000286                       # m
 system.cpu.dcache.WriteReq_mshr_misses           1859                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               11923.977948                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55045.863695                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26494968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       128422000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 55046.272494                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26494967                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       128478000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000088                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2333                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  2334                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    121423000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    121476000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000088                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2333                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             2334                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55045.863695                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55046.272494                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26494968                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      128422000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               26494967                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      128478000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000088                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2333                       # number of overall misses
+system.cpu.dcache.overall_misses                 2334                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    121423000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    121476000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000088                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2333                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            2334                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                    157                       # number of replacements
-system.cpu.dcache.sampled_refs                   2222                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1441.023190                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26495079                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1442.022508                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
 system.cpu.dtb.accesses                      26497334                       # DTB accesses
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   6681                       # number of replacements
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1418.026644                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1418.025998                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses              1748                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency     69920000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses         1748                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              8984                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses              8985                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  5942                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     158184000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.338602                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                3042                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    121680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338602                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           3042                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency     158236000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.338676                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                3043                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    121720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338676                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           3043                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses            111                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
@@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses             104                       # nu
 system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.970090                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.969435                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              10732                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses              10733                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                   5942                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      249080000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.446329                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4790                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency      249132000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.446380                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4791                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    191600000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.446329                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4790                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    191640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.446380                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4791                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses             10732                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                  5942                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     249080000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.446329                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4790                       # number of overall misses
+system.cpu.l2cache.overall_miss_latency     249132000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.446380                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4791                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    191600000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.446329                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4790                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    191640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.446380                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4791                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -235,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3009                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3010                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2021.060296                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2022.059349                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    5928                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        237494382                       # number of cpu cycles simulated
+system.cpu.numCycles                        237494492                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
 system.cpu.num_refs                          26537141                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls