diff options
author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/long/70.twolf/ref/alpha/tru64/simple-timing | |
parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/simple-timing')
4 files changed, 65 insertions, 64 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 0190cf0fe..0a4a7ae02 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index a1b1d8e71..58a892eca 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1053450 # Simulator instruction rate (inst/s) -host_mem_usage 201692 # Number of bytes of host memory used -host_seconds 87.24 # Real time elapsed on the host -host_tick_rate 1359521857 # Simulator tick rate (ticks/s) +host_inst_rate 1888440 # Simulator instruction rate (inst/s) +host_mem_usage 205224 # Number of bytes of host memory used +host_seconds 48.67 # Real time elapsed on the host +host_tick_rate 2440025498 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118605 # Number of seconds simulated -sim_ticks 118605062000 # Number of ticks simulated +sim_seconds 0.118747 # Number of seconds simulated +sim_ticks 118747191000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2333 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 91903090 # ITB hits system.cpu.itb.misses 47 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4790 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237210124 # number of cpu cycles simulated +system.cpu.numCycles 237494382 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index 26249ed90..337694eda 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7004 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index a512928ef..77554b01e 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:15:31 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:07:25 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 |