Update Alpha reference stats for clock changes.

tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
    Update refs for clock changes.

--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42

5 files changed, 59 insertions, 108 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index e2265235e..cd04983c0 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -1,33 +1,7 @@
 [root]
 type=Root
 children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
 
 [system]
 type=System
@@ -38,7 +12,7 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
 cpu_id=0
 defer_registration=false
 function_trace=false
@@ -182,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 euid=100
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
index fcf06c7db..3089af658 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
@@ -1,9 +1,6 @@
 [root]
 type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
 
 [system.physmem]
 type=PhysicalMemory
@@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 system=system
 uid=100
 euid=100
@@ -50,7 +47,7 @@ progress_interval=0
 system=system
 cpu_id=0
 workload=system.cpu.workload
-clock=1
+clock=500
 phase=0
 defer_registration=false
 // width not specified
@@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index 5cdae9c4a..b45fb965e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 607322                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 157212                       # Number of bytes of host memory used
-host_seconds                                   151.33                       # Real time elapsed on the host
-host_tick_rate                                1013960                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 335846                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156240                       # Number of bytes of host memory used
+host_seconds                                   273.71                       # Real time elapsed on the host
+host_tick_rate                              216396349                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903057                       # Number of instructions simulated
-sim_seconds                                  0.000153                       # Number of seconds simulated
-sim_ticks                                   153438012                       # Number of ticks simulated
+sim_seconds                                  0.059229                       # Number of seconds simulated
+sim_ticks                                 59229023000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3701.356540                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2701.356540                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency  3629.746835                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2629.746835                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               19995724                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        1754443                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        1720500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  474                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1280443                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      1246500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             474                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3869.070366                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2869.070366                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency  3602.116705                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2602.116705                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       6763135                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       6296500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      5015135                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      4548500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3833.293429                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2833.293429                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency  3608.010801                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2608.010801                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                26495079                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         8517578                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency         8017000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                  2222                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      6295578                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      5795000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses             2222                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3833.293429                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2833.293429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency  3608.010801                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2608.010801                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               26495079                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        8517578                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency        8017000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                 2222                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      6295578                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      5795000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            2222                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.sampled_refs                   2222                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1398.130089                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1441.710869                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495079                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
 system.cpu.icache.ReadReq_accesses           91903058                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3117.603760                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2117.603760                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  3077.908343                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2077.908343                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               91894548                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       26530808                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       26193000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000093                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 8510                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     18020808                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     17683000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000093                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            8510                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            91903058                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3117.603760                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2117.603760                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency  3077.908343                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2077.908343                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                91894548                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        26530808                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        26193000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000093                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  8510                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     18020808                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     17683000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000093                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             8510                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses           91903058                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3117.603760                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2117.603760                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency  3077.908343                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2077.908343                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               91894548                       # number of overall hits
-system.cpu.icache.overall_miss_latency       26530808                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       26193000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000093                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 8510                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     18020808                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     17683000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000093                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            8510                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   6681                       # number of replacements
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1374.520503                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1418.735069                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 91894548                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses             10732                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2892.483207                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1885.503778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency  2703.820319                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1702.820319                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  5968                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      13779790                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      12881000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.443906                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                4764                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      8982540                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency      8112236                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.443906                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           4764                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
@@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses              10732                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2892.483207                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1885.503778                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency  2703.820319                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1702.820319                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                   5968                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       13779790                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency       12881000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.443906                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 4764                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency      8982540                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency      8112236                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.443906                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses            4764                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses             10836                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2892.483207                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1885.503778                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency  2703.820319                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1702.820319                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                  6072                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      13779790                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency      12881000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.439646                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                4764                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      8982540                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency      8112236                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.439646                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses           4764                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  4764                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3073.845977                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3173.029647                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    6072                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        153438012                       # number of cpu cycles simulated
+system.cpu.numCycles                      59229023000                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903057                       # Number of instructions executed
 system.cpu.num_refs                          26537109                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
index 00387ae5c..98777e0af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
@@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1
   I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
   1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
   2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
-  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.3  0.0     0     46
   4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
   5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
   6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
@@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1
  37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
  38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
  39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
- 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.3 47.5  0.0     0     48
  41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
  42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
  43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
index eb1796ead..f33d007a7 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
@@ -1,2 +1,2 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
+warn: Increasing stack size by one page.