stats: update stats for preceding coherence changes

Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.

4 files changed, 64 insertions, 57 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 408aa067d..3a1e6de05 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -152,12 +152,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
index b2d79346c..67f69f09d 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
@@ -1,2 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index 927d0a698..258e66688 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:41:35
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:58:58
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -26,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 
\ No newline at end of file
+122 123 124 Exiting @ tick 118742021000 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index ab73f2477..b08531811 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 611509                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195576                       # Number of bytes of host memory used
-host_seconds                                   150.29                       # Real time elapsed on the host
-host_tick_rate                              790125098                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1269659                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210612                       # Number of bytes of host memory used
+host_seconds                                    72.38                       # Real time elapsed on the host
+host_tick_rate                             1640438984                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
-sim_seconds                                  0.118747                       # Number of seconds simulated
-sim_ticks                                118747246000                       # Number of ticks simulated
+sim_seconds                                  0.118742                       # Number of seconds simulated
+sim_ticks                                118742021000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211                       # average ReadReq mshr miss latency
@@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses             475                       # nu
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6499244                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     104104000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000286                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1859                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     98527000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000286                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1859                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits               6499339                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      98784000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000271                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                1764                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     93492000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000271                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1764                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
@@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55046.272494                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26494967                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       128478000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000088                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2334                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55005.806163                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26495062                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       123158000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  2239                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    121476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000088                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2334                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency    116441000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses             2239                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.352056                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1442.022508                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.352059                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1442.035674                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55046.272494                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55005.806163                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26494967                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      128478000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000088                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2334                       # number of overall misses
+system.cpu.dcache.overall_hits               26495062                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      123158000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 2239                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    121476000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000088                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2334                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency    116441000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses            2239                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1442.022508                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1442.035674                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses             8510                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.692396                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1418.025998                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.692403                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1418.041181                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   6681                       # number of replacements
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1418.025998                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1418.041181                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -180,20 +180,20 @@ system.cpu.l2cache.ReadReq_misses                3043                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency    121720000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338676                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3043                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses            111                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses             16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      5772000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency       832000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses              111                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      4440000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses               16                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       640000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses          111                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses           16                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.969435                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.909179                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -213,10 +213,10 @@ system.cpu.l2cache.demand_mshr_misses            4791                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.061290                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0                  0.062752                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_%::1                  0.000419                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2008.334369                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            13.724981                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0          2056.260143                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            13.724287                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -232,14 +232,14 @@ system.cpu.l2cache.overall_mshr_misses           4791                       # nu
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3010                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3105                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2022.059349                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2069.984431                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    5928                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        237494492                       # number of cpu cycles simulated
+system.cpu.numCycles                        237484042                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
 system.cpu.num_refs                          26537141                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls