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authorAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
commit9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch)
tree79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/long/70.twolf/ref/alpha/tru64
parent77853b9f529947c3a9db78ef3458289f387289ce (diff)
downloadgem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64')
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt11
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index e64185111..6d564a58f 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 15 2010 08:52:32
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 13:43:59
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:30:09
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 548b29280..6e4f9aea5 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 130193 # Simulator instruction rate (inst/s)
-host_mem_usage 210712 # Number of bytes of host memory used
-host_seconds 646.58 # Real time elapsed on the host
-host_tick_rate 62840883 # Simulator tick rate (ticks/s)
+host_inst_rate 134338 # Simulator instruction rate (inst/s)
+host_mem_usage 210480 # Number of bytes of host memory used
+host_seconds 626.63 # Real time elapsed on the host
+host_tick_rate 64841631 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040632 # Number of seconds simulated
@@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 7182981 # DT
system.cpu.dtb.write_misses 1041 # DTB write misses
system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched
-system.cpu.fetch.Cycles 49623738 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 30564219 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss