diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/70.twolf/ref/alpha/tru64 | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64')
3 files changed, 389 insertions, 387 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index cbca14c5b..249041a4d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 43a475337..2583cc940 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,10 +3,12 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:49:49 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 30278595500 because target called exit() +122 123 124 Exiting @ tick 29167093500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 08d328376..f77f26233 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030279 # Number of seconds simulated -sim_ticks 30278595500 # Number of ticks simulated +sim_seconds 0.029167 # Number of seconds simulated +sim_ticks 29167093500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116969 # Simulator instruction rate (inst/s) -host_tick_rate 42072708 # Simulator tick rate (ticks/s) -host_mem_usage 256296 # Number of bytes of host memory used -host_seconds 719.67 # Real time elapsed on the host +host_inst_rate 127298 # Simulator instruction rate (inst/s) +host_tick_rate 44106983 # Simulator tick rate (ticks/s) +host_mem_usage 209296 # Number of bytes of host memory used +host_seconds 661.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25688278 # DTB read hits -system.cpu.dtb.read_misses 550762 # DTB read misses +system.cpu.dtb.read_hits 25236325 # DTB read hits +system.cpu.dtb.read_misses 540509 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26239040 # DTB read accesses -system.cpu.dtb.write_hits 7360758 # DTB write hits -system.cpu.dtb.write_misses 1044 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7361802 # DTB write accesses -system.cpu.dtb.data_hits 33049036 # DTB hits -system.cpu.dtb.data_misses 551806 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 33600842 # DTB accesses -system.cpu.itb.fetch_hits 19370237 # ITB hits -system.cpu.itb.fetch_misses 82 # ITB misses +system.cpu.dtb.read_accesses 25776834 # DTB read accesses +system.cpu.dtb.write_hits 7362909 # DTB write hits +system.cpu.dtb.write_misses 1032 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7363941 # DTB write accesses +system.cpu.dtb.data_hits 32599234 # DTB hits +system.cpu.dtb.data_misses 541541 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 33140775 # DTB accesses +system.cpu.itb.fetch_hits 18604047 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 19370319 # ITB accesses +system.cpu.itb.fetch_accesses 18604132 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 60557192 # number of cpu cycles simulated +system.cpu.numCycles 58334188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18972162 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14043194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1908534 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15684343 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12020738 # Number of BTB hits +system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1817403 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 20660360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 162109118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18972162 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13838141 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 29871214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8831306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3272537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 19370237 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 684277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.681098 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.259568 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 30592486 50.60% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2950542 4.88% 55.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2105012 3.48% 58.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3386904 5.60% 64.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4238557 7.01% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1492876 2.47% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1782148 2.95% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1645056 2.72% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12270119 20.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313293 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.676959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22547787 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2537266 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 28115662 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 618580 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6644405 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2987075 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13654 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 155918946 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42842 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6644405 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24245198 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 523469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 27028766 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2015831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148832808 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 266593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1498062 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 109279851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 192445710 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 181748286 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10697424 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40852490 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 518 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 515 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6036784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30729381 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9521294 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2640558 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 881343 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 123679327 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 494 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105899114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 512588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38384232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30395152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 105 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60463700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.751449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825920 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21057299 34.83% 34.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11707934 19.36% 54.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9587960 15.86% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925941 11.45% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5557420 9.19% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2847009 4.71% 95.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1835835 3.04% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796714 1.32% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147588 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60463700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186761 11.23% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 209 0.01% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6487 0.39% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3444 0.21% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845716 50.84% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 517920 31.13% 93.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103033 6.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 64090689 60.52% 60.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 486042 0.46% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799885 2.64% 63.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114989 0.11% 63.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411237 2.28% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311681 0.29% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763573 0.72% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27425152 25.90% 92.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7495540 7.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105899114 # Type of FU issued -system.cpu.iq.rate 1.748745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1663570 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015709 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 259207602 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 152594620 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93309235 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15230484 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9878183 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7072078 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 99520074 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8042603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1240194 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued +system.cpu.iq.rate 1.798857 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10733183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14770 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 472388 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3020191 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10319 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6644405 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16385 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 135563884 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 881728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30729381 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9521294 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 494 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 472388 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1792269 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 350241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2142510 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 103141866 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26239584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2757248 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11884063 # number of nop insts executed -system.cpu.iew.exec_refs 33601488 # number of memory reference insts executed -system.cpu.iew.exec_branches 12972684 # Number of branches executed -system.cpu.iew.exec_stores 7361904 # Number of stores executed -system.cpu.iew.exec_rate 1.703214 # Inst execution rate -system.cpu.iew.wb_sent 101639951 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 100381313 # cumulative count of insts written-back -system.cpu.iew.wb_producers 68069676 # num instructions producing a value -system.cpu.iew.wb_consumers 93955815 # num instructions consuming a value +system.cpu.iew.exec_nop 11799539 # number of nop insts executed +system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed +system.cpu.iew.exec_branches 12916232 # Number of branches executed +system.cpu.iew.exec_stores 7364040 # Number of stores executed +system.cpu.iew.exec_rate 1.754258 # Inst execution rate +system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67789343 # num instructions producing a value +system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.657628 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724486 # average fanout of values written-back +system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 43662883 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 53819295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.707623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.466902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24819499 46.12% 46.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11624197 21.60% 67.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5120039 9.51% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2844700 5.29% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1712935 3.18% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1498439 2.78% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 822147 1.53% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 790849 1.47% 91.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4586490 8.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 53819295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4586490 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 184797703 # The number of ROB reads -system.cpu.rob.rob_writes 277819902 # The number of ROB writes -system.cpu.timesIdled 2285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 180051805 # The number of ROB reads +system.cpu.rob.rob_writes 271380444 # The number of ROB writes +system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.719380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.719380 # CPI: Total CPI of All Threads -system.cpu.ipc 1.390086 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.390086 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 139300854 # number of integer regfile reads -system.cpu.int_regfile_writes 75996636 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185785 # number of floating regfile reads -system.cpu.fp_regfile_writes 6053506 # number of floating regfile writes -system.cpu.misc_regfile_reads 715599 # number of misc regfile reads +system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 138495671 # number of integer regfile reads +system.cpu.int_regfile_writes 75435014 # number of integer regfile writes +system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes +system.cpu.misc_regfile_reads 715554 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8657 # number of replacements -system.cpu.icache.tagsinuse 1596.063648 # Cycle average of tags in use -system.cpu.icache.total_refs 19358424 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1827.990935 # Average number of references to valid blocks. +system.cpu.icache.replacements 8695 # number of replacements +system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use +system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1596.063648 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779328 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 19358424 # number of ReadReq hits -system.cpu.icache.demand_hits 19358424 # number of demand (read+write) hits -system.cpu.icache.overall_hits 19358424 # number of overall hits -system.cpu.icache.ReadReq_misses 11813 # number of ReadReq misses -system.cpu.icache.demand_misses 11813 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11813 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188211000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 19370237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 19370237 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 19370237 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000610 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000610 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000610 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15932.531956 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15932.531956 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15932.531956 # average overall miss latency +system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses +system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124783500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000547 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000547 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000547 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11783.144476 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 156 # number of replacements -system.cpu.dcache.tagsinuse 1459.699326 # Cycle average of tags in use -system.cpu.dcache.total_refs 30929897 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2239 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13814.156766 # Average number of references to valid blocks. +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use +system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.699326 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24436799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 42 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30929855 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30929855 # number of overall hits -system.cpu.dcache.ReadReq_misses 922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8047 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8969 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8969 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27935000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289776500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 317711500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 317711500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24437721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30938824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30938824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.023256 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30298.264642 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36010.500808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35423.291337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35423.291337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,73 +410,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6731 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6731 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2238 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2238 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77915000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77915000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.023256 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32233.201581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35568.706697 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2399.023561 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7622 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.145833 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2381.411279 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.612282 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072675 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7611 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7636 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7636 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3486 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5193 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5193 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119743000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59251500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178994500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11097 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12829 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12829 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.314139 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985566 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.404786 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.404786 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.684452 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34710.896309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34468.419026 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34468.419026 # average overall miss latency +system.cpu.l2cache.demand_hits 7680 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7680 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3488 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119792500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59244000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 179036500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 179036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.403449 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.403449 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34469.869080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34469.869080 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5193 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5193 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108417500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53859000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162276500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162276500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.404786 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.404786 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100.831899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31551.845343 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |