diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/70.twolf/ref/alpha/tru64 | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64')
11 files changed, 250 insertions, 243 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 8ab14c5fa..84850f694 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index d80de6314..21f9ae246 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 19:04:15 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:01:01 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index b78683303..53d449590 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 137731 # Simulator instruction rate (inst/s) -host_mem_usage 254052 # Number of bytes of host memory used -host_seconds 667.27 # Real time elapsed on the host -host_tick_rate 60742348 # Simulator tick rate (ticks/s) +host_inst_rate 197293 # Simulator instruction rate (inst/s) +host_mem_usage 267004 # Number of bytes of host memory used +host_seconds 465.82 # Real time elapsed on the host +host_tick_rate 87010339 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated sim_ticks 40531279000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 59.146483 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 7590519 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 11539980 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 57928840 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 84258569 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.activity 91.670040 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 27308571 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 59.146483 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 4489525 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 7590519 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 138 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 2806970 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 7883251 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 11539980 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.execution_unit.executions 57928840 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 7433715 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 9804 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 4938 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066327 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 2191.171348 # Cy system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 458252 # Number of Multipy Operations Executed system.cpu.numCycles 81062559 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 84258569 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 68427361 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 27951091 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 53111468 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 33262621 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 47799938 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 32674404 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 48388155 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63236282 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 17826277 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 26883065 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 54179494 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 27951091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53111468 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33262621 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 47799938 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 32674404 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 48388155 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63236282 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 17826277 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 26883065 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 54179494 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 0fa57e7b8..9d0ac975a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index c1340f659..ec6c3f639 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:40 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c969dd1c3..8dc1a35af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141441 # Simulator instruction rate (inst/s) -host_mem_usage 212592 # Number of bytes of host memory used -host_seconds 595.16 # Real time elapsed on the host -host_tick_rate 57448767 # Simulator tick rate (ticks/s) +host_inst_rate 274016 # Simulator instruction rate (inst/s) +host_mem_usage 208580 # Number of bytes of host memory used +host_seconds 307.21 # Real time elapsed on the host +host_tick_rate 111296260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.034191 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1952481 # Nu system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3636559 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:count 91903055 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. -system.cpu.commit.COM:int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.COM:loads 19996198 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 26497301 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 2243 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 1459.544584 # Cy system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 25031 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle +system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 32239873 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 31883201 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 10134 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 17386201 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12448390 # Number of branches executed -system.cpu.iew.EXEC:nop 11194543 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.455255 # Inst execution rate -system.cpu.iew.EXEC:refs 32240280 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7278167 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 87558338 # num instructions consuming a value -system.cpu.iew.WB:count 97422402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.737743 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 64595544 # num instructions producing a value -system.cpu.iew.WB:rate 1.424676 # insts written-back per cycle -system.cpu.iew.WB:sent 98290476 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 12448390 # Number of branches executed +system.cpu.iew.exec_nop 11194543 # number of nop insts executed +system.cpu.iew.exec_rate 1.455255 # Inst execution rate +system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed +system.cpu.iew.exec_stores 7278167 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 2710213 # system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 64595544 # num instructions producing a value +system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle +system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 134796814 # number of integer regfile reads system.cpu.int_regfile_writes 73485618 # number of integer regfile writes system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1618550 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.490981 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 30709271 # Nu system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.rate 1.490981 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 5098 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency @@ -477,27 +477,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 68382153 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 9732280 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 457 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 186605606 # The number of ROB reads system.cpu.rob.rob_writes 260771760 # The number of ROB writes system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 06628f244..8a2d657fe 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 3667c8fef..17088cdf6 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1609489 # Simulator instruction rate (inst/s) -host_mem_usage 222008 # Number of bytes of host memory used -host_seconds 57.10 # Real time elapsed on the host -host_tick_rate 804741446 # Simulator tick rate (ticks/s) +host_inst_rate 5556970 # Simulator instruction rate (inst/s) +host_mem_usage 199664 # Number of bytes of host memory used +host_seconds 16.54 # Real time elapsed on the host +host_tick_rate 2778455792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cab9a523d..f2a594baf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 5503045c3..c82977f3d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:48 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:08 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 2aaa18b18..ea7e649f7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 559604 # Simulator instruction rate (inst/s) -host_mem_usage 229724 # Number of bytes of host memory used -host_seconds 164.23 # Real time elapsed on the host -host_tick_rate 723015392 # Simulator tick rate (ticks/s) +host_inst_rate 2623121 # Simulator instruction rate (inst/s) +host_mem_usage 207408 # Number of bytes of host memory used +host_seconds 35.04 # Real time elapsed on the host +host_tick_rate 3389091421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 4765 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- |