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authorSteve Reinhardt <stever@gmail.com>2008-08-03 18:13:29 -0400
committerSteve Reinhardt <stever@gmail.com>2008-08-03 18:13:29 -0400
commit62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch)
tree739253709735d1a8b5da963d2230a5418779d297 /tests/long/70.twolf/ref/alpha
parentb179c3f4cd1e89872de34d70105f703e72377029 (diff)
downloadgem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha')
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini3
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt602
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout8
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini3
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt116
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout8
8 files changed, 373 insertions, 371 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index dbf63ca05..3d1cca219 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -368,6 +368,7 @@ cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
+errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
@@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index 4231c8e95..36295ae14 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 13021521 # Number of BTB hits
-global.BPredUnit.BTBLookups 16952662 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1212 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1950052 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted
-global.BPredUnit.lookups 19451761 # Number of BP lookups
-global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target.
-host_inst_rate 82033 # Simulator instruction rate (inst/s)
-host_mem_usage 156240 # Number of bytes of host memory used
-host_seconds 1026.17 # Real time elapsed on the host
-host_tick_rate 39719192 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 10604217 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 13008791 # Number of BTB hits
+global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
+global.BPredUnit.lookups 19468548 # Number of BP lookups
+global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
+host_inst_rate 157592 # Simulator instruction rate (inst/s)
+host_mem_usage 206456 # Number of bytes of host memory used
+host_seconds 534.16 # Real time elapsed on the host
+host_tick_rate 76416157 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.040758 # Number of seconds simulated
-sim_ticks 40758469000 # Number of ticks simulated
+sim_seconds 0.040819 # Number of seconds simulated
+sim_ticks 40818658500 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2850471 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 73485570
+system.cpu.commit.COM:committed_per_cycle.samples 73457195
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 36241200 4931.74%
- 1 18077968 2460.07%
- 2 7549008 1027.28%
- 3 4015107 546.38%
- 4 2030060 276.25%
- 5 1302937 177.31%
- 6 688676 93.72%
- 7 730143 99.36%
- 8 2850471 387.90%
+ 0 36278942 4938.79%
+ 1 18156305 2471.69%
+ 2 7455514 1014.95%
+ 3 3880418 528.26%
+ 4 2046448 278.59%
+ 5 1301140 177.13%
+ 6 721823 98.26%
+ 7 760802 103.57%
+ 8 2855803 388.77%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1937588 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 55772540 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 0.968368 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 23271115 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 9301.109350 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 631 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 7925.428784 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 8046 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13269.627731 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29772218 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 8025.469632 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 8677 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2362 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29772218 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 8025.469632 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29763541 # number of overall hits
-system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 8677 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 29894354 # number of overall hits
+system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9171 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2362 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -121,103 +121,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 159 # number of replacements
-system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29763775 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 105 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12627 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3048985 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 162336287 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 39537926 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 29896024 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 8028470 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45209 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 189320 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 31783723 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 31911121 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 31332689 # DTB hits
-system.cpu.dtb.misses 451034 # DTB misses
-system.cpu.dtb.read_accesses 24575603 # DTB read accesses
+system.cpu.dtb.hits 31454022 # DTB hits
+system.cpu.dtb.misses 457099 # DTB misses
+system.cpu.dtb.read_accesses 24718123 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 24125563 # DTB read hits
-system.cpu.dtb.read_misses 450040 # DTB read misses
-system.cpu.dtb.write_accesses 7208120 # DTB write accesses
+system.cpu.dtb.read_hits 24262026 # DTB read hits
+system.cpu.dtb.read_misses 456097 # DTB read misses
+system.cpu.dtb.write_accesses 7192998 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 7207126 # DTB write hits
-system.cpu.dtb.write_misses 994 # DTB write misses
-system.cpu.fetch.Branches 19451761 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 19219800 # Number of cache lines fetched
-system.cpu.fetch.Cycles 50154718 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 536931 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 167137455 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2059472 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.238622 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 19219800 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 14743121 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.050340 # Number of inst fetches per cycle
+system.cpu.dtb.write_hits 7191996 # DTB write hits
+system.cpu.dtb.write_misses 1002 # DTB write misses
+system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched
+system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 81514041
+system.cpu.fetch.rateDist.samples 81528342
system.cpu.fetch.rateDist.min_value 0
- 0 50579197 6204.97%
- 1 3119637 382.71%
- 2 2009848 246.56%
- 3 3519871 431.81%
- 4 4617609 566.48%
- 5 1511564 185.44%
- 6 2006119 246.11%
- 7 1828029 224.26%
- 8 12322167 1511.66%
+ 0 50560377 6201.57%
+ 1 3114212 381.98%
+ 2 2012618 246.86%
+ 3 3505366 429.96%
+ 4 4590613 563.07%
+ 5 1506961 184.84%
+ 6 2028359 248.79%
+ 7 1846743 226.52%
+ 8 12363093 1516.42%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 19219800 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 6448.716735 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000549 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10559 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10102 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1901.528509 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 19219800 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 6448.716735 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
-system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000549 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10559 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10102 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
+system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses
+system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 19219800 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 6448.716735 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 19209241 # number of overall hits
-system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000549 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10559 # number of overall misses
-system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10102 # number of overall MSHR misses
+system.cpu.icache.overall_hits 19218965 # number of overall hits
+system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses
+system.cpu.icache.overall_misses 11038 # number of overall misses
+system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8191 # number of replacements
-system.cpu.icache.sampled_refs 10102 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8143 # number of replacements
+system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1547.575549 # Cycle average of tags in use
-system.cpu.icache.total_refs 19209241 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use
+system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 2898 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12781978 # Number of branches executed
-system.cpu.iew.EXEC:nop 12589139 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.246896 # Inst execution rate
-system.cpu.iew.EXEC:refs 31834864 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7209747 # Number of stores executed
+system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
+system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
+system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 91092089 # num instructions consuming a value
-system.cpu.iew.WB:count 99774116 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.721851 # average fanout of values written-back
+system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value
+system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 65754876 # num instructions producing a value
-system.cpu.iew.WB:rate 1.223968 # insts written-back per cycle
-system.cpu.iew.WB:sent 100649675 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2112266 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 284242 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 33854360 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1723654 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 10604217 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 147674740 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24625117 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2113526 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 101643128 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 120911 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 65837671 # num instructions producing a value
+system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
+system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 8028470 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 165624 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 844640 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2772 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 223466 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 13819947 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4101522 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 223466 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 201477 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1910789 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.032665 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.032665 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 103756654 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 7 0.00% # Type of FU issued
- IntAlu 64328227 62.00% # Type of FU issued
- IntMult 474807 0.46% # Type of FU issued
+ IntAlu 64430040 61.93% # Type of FU issued
+ IntMult 475055 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2783435 2.68% # Type of FU issued
- FloatCmp 115619 0.11% # Type of FU issued
- FloatCvt 2381566 2.30% # Type of FU issued
- FloatMult 305730 0.29% # Type of FU issued
- FloatDiv 755065 0.73% # Type of FU issued
- FloatSqrt 322 0.00% # Type of FU issued
- MemRead 25279956 24.36% # Type of FU issued
- MemWrite 7331920 7.07% # Type of FU issued
+ FloatAdd 2782164 2.67% # Type of FU issued
+ FloatCmp 115645 0.11% # Type of FU issued
+ FloatCvt 2377276 2.29% # Type of FU issued
+ FloatMult 305748 0.29% # Type of FU issued
+ FloatDiv 755245 0.73% # Type of FU issued
+ FloatSqrt 323 0.00% # Type of FU issued
+ MemRead 25462424 24.48% # Type of FU issued
+ MemWrite 7324714 7.04% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1948888 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018783 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 297234 15.25% # attempts to use FU when none available
+ IntAlu 274346 14.19% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 492 0.03% # attempts to use FU when none available
+ FloatAdd 31 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 3359 0.17% # attempts to use FU when none available
- FloatMult 1274 0.07% # attempts to use FU when none available
- FloatDiv 828421 42.51% # attempts to use FU when none available
+ FloatCvt 6547 0.34% # attempts to use FU when none available
+ FloatMult 2333 0.12% # attempts to use FU when none available
+ FloatDiv 832912 43.09% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 745957 38.28% # attempts to use FU when none available
- MemWrite 72151 3.70% # attempts to use FU when none available
+ MemRead 743147 38.44% # attempts to use FU when none available
+ MemWrite 73812 3.82% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 81514041
+system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 35401194 4342.96%
- 1 18638593 2286.55%
- 2 11850080 1453.75%
- 3 6738129 826.62%
- 4 5072118 622.24%
- 5 2314380 283.92%
- 6 1219789 149.64%
- 7 213656 26.21%
- 8 66102 8.11%
+ 0 35305774 4330.49%
+ 1 18904883 2318.81%
+ 2 11574998 1419.75%
+ 3 6762756 829.50%
+ 4 5075415 622.53%
+ 5 2394533 293.71%
+ 6 1208963 148.29%
+ 7 250769 30.76%
+ 8 50251 6.16%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.272823 # Inst issue rate
-system.cpu.iq.iqInstsAdded 135085172 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 103756654 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 50298713 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 225846 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 47102449 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 19219874 # ITB accesses
+system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate
+system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 19230073 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 19219800 # ITB hits
-system.cpu.itb.misses 74 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 5751.440092 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2751.440092 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 9984500 # number of ReadExReq miss cycles
+system.cpu.itb.hits 19230003 # ITB hits
+system.cpu.itb.misses 70 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4776500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 10609 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 5363.488784 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.488784 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 18171500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.319351 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8007500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319351 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 122 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 5704.918033 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2704.918033 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 696000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 122 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 330000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 122 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.154260 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12345 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 5494.925839 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 28156000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.415067 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 12784000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.415067 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12345 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 5494.925839 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7221 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 28156000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.415067 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5124 # number of overall misses
+system.cpu.l2cache.overall_hits 7186 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5110 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 12784000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.415067 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -419,30 +419,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2257.557113 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7206 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 81516939 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 1780351 # Number of cycles rename is blocking
+system.cpu.numCycles 81637318 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1047628 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 40793393 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 942240 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 202632347 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 157116893 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 115707927 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 28822360 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 8028470 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 2084695 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 47280566 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 4772 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 463 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4626500 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed
-system.cpu.timesIdled 687 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed
+system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
index 5992f7131..8053728f7 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index 20e9ee506..d1a734653 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:14:27 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:15:05 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 0190cf0fe..0a4a7ae02 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -166,6 +166,7 @@ cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
egid=100
env=
+errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
@@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index a1b1d8e71..58a892eca 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1053450 # Simulator instruction rate (inst/s)
-host_mem_usage 201692 # Number of bytes of host memory used
-host_seconds 87.24 # Real time elapsed on the host
-host_tick_rate 1359521857 # Simulator tick rate (ticks/s)
+host_inst_rate 1888440 # Simulator instruction rate (inst/s)
+host_mem_usage 205224 # Number of bytes of host memory used
+host_seconds 48.67 # Real time elapsed on the host
+host_tick_rate 2440025498 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.118605 # Number of seconds simulated
-sim_ticks 118605062000 # Number of ticks simulated
+sim_seconds 0.118747 # Number of seconds simulated
+sim_ticks 118747191000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26494968 # number of overall hits
-system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2333 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 91894580 # number of overall hits
-system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
system.cpu.itb.hits 91903090 # ITB hits
system.cpu.itb.misses 47 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
@@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5942 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4790 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 237210124 # number of cpu cycles simulated
+system.cpu.numCycles 237494382 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
index 26249ed90..337694eda 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
+0: system.remote_gdb.listener: listening for remote gdb on port 7004
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index a512928ef..77554b01e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:15:31 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:07:25 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2