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authorNathan Binkert <nate@binkert.org>2008-07-22 17:00:18 -0400
committerNathan Binkert <nate@binkert.org>2008-07-22 17:00:18 -0400
commita8df952dd38cb686c6a795480630649aa51fd894 (patch)
tree380126490f459a4bef6a485cbda2b8efa4ae085e /tests/long/70.twolf/ref/alpha
parentaa2bb4f7b9ec571a4430da25173fbb76d1b0c8bb (diff)
downloadgem5-a8df952dd38cb686c6a795480630649aa51fd894.tar.xz
tests: update config.ini and stdout for the various tests.
These files were a bit too out of date and resulted in a bit of confusion.
Diffstat (limited to 'tests/long/70.twolf/ref/alpha')
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini2
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout16
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini8
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout16
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini3
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout16
6 files changed, 60 insertions, 1 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 945804e3d..dbf63ca05 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
type=PhysicalMemory
file=
latency=1
+latency_var=0
+null=false
range=0:134217727
zero=false
port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index f32f0a972..20e9ee506 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:27 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 8fbd6f60b..f0ed922b1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
@@ -54,9 +55,11 @@ euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
+max_stack_size=67108864
output=cout
pid=100
ppid=99
+simpoint=0
system=system
uid=100
@@ -65,6 +68,7 @@ type=Bus
block_size=64
bus_id=0
clock=1000
+header_cycles=1
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
type=PhysicalMemory
file=
latency=1
+latency_var=0
+null=false
range=0:134217727
zero=false
port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f32f0a972..0fc73d0d9 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index fd50e16e0..0190cf0fe 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
output=cout
pid=100
ppid=99
+simpoint=0
system=system
uid=100
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
type=PhysicalMemory
file=
latency=1
+latency_var=0
+null=false
range=0:134217727
zero=false
port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index f32f0a972..a512928ef 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:15:31 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program