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authorAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
commitd114e5fae6ffb83a1145208532def7654cc9dd75 (patch)
treed54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/70.twolf/ref/alpha
parent02353a60ee6ce831302067aae38bc31b739f14e5 (diff)
downloadgem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz
Regression: Update stats for cache changes.
--HG-- extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/70.twolf/ref/alpha')
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini72
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt581
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini38
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt187
4 files changed, 464 insertions, 414 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 72c4312d9..752831326 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -74,8 +75,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -107,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@@ -206,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@@ -218,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@@ -248,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -260,21 +269,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -282,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -320,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -343,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
@@ -366,7 +374,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index 8dcfd61cf..f4a8bde29 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 11874522 # Number of BTB hits
-global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted
-global.BPredUnit.lookups 17824174 # Number of BP lookups
-global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target.
-host_inst_rate 74830 # Simulator instruction rate (inst/s)
-host_mem_usage 156844 # Number of bytes of host memory used
-host_seconds 1124.95 # Real time elapsed on the host
-host_tick_rate 39347975 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 13022932 # Number of BTB hits
+global.BPredUnit.BTBLookups 16938031 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1944645 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 14588431 # Number of conditional branches predicted
+global.BPredUnit.lookups 19441115 # Number of BP lookups
+global.BPredUnit.usedRAS 1715741 # Number of times the RAS was used to get a target.
+host_inst_rate 140839 # Simulator instruction rate (inst/s)
+host_mem_usage 205524 # Number of bytes of host memory used
+host_seconds 597.70 # Real time elapsed on the host
+host_tick_rate 68085854 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 17320747 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 5158870 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 33916617 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 10592327 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.044264 # Number of seconds simulated
-sim_ticks 44264420500 # Number of ticks simulated
+sim_seconds 0.040695 # Number of seconds simulated
+sim_ticks 40694900000 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2814383 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 81602250
+system.cpu.commit.COM:committed_per_cycle.samples 73372540
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 44887304 5500.74%
- 1 17052684 2089.73%
- 2 8186225 1003.19%
- 3 3991011 489.08%
- 4 1764745 216.26%
- 5 1325913 162.48%
- 6 892255 109.34%
- 7 554091 67.90%
- 8 2948022 361.27%
+ 0 36054158 4913.85%
+ 1 18224800 2483.87%
+ 2 7501822 1022.43%
+ 3 3901009 531.67%
+ 4 2128189 290.05%
+ 5 1274528 173.71%
+ 6 744433 101.46%
+ 7 729218 99.39%
+ 8 2814383 383.57%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1932230 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 55717434 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
+system.cpu.cpi 0.966851 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.966851 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 23356209 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 9066 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5569 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23355709 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4533000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000021 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 500 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2784500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 500 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6495002 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 24564.959569 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5850.134771 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6493147 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 45568000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6101 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 10852000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 13325.436607 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 29851211 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 21274.309979 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29848856 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 50101000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2355 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6224 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13636500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2355 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 29851211 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 21274.309979 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29540842 # number of overall hits
-system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 7956 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 29848856 # number of overall hits
+system.cpu.dcache.overall_miss_latency 50101000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2355 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6224 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13636500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2355 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 163 # number of replacements
-system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 160 # number of replacements
+system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1458.130010 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29848978 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 107 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched
-system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 106 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3820626 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12575 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3037417 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 162462210 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 39463165 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 29936850 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8016661 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 44953 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 151900 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 19441115 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 19217268 # Number of cache lines fetched
+system.cpu.fetch.Cycles 50163624 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 510483 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 167309935 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2078673 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.238866 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 19217268 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 14738673 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.055677 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 88528924
+system.cpu.fetch.rateDist.samples 81389202
system.cpu.fetch.rateDist.min_value 0
- 0 61853767 6986.84%
- 1 2838595 320.64%
- 2 1299355 146.77%
- 3 1865057 210.67%
- 4 3537974 399.64%
- 5 1231942 139.16%
- 6 1400771 158.23%
- 7 1171977 132.38%
- 8 13329486 1505.66%
+ 0 50442849 6197.73%
+ 1 3127409 384.25%
+ 2 2013333 247.37%
+ 3 3501649 430.24%
+ 4 4585592 563.42%
+ 5 1499931 184.29%
+ 6 2042041 250.90%
+ 7 1854540 227.86%
+ 8 12321858 1513.94%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 19216915 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5291.898608 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3156.958250 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 19206855 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 53236500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 10060 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 353 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 31759000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10060 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1909.230119 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
-system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 19216915 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5291.898608 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
+system.cpu.icache.demand_hits 19206855 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 53236500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses
+system.cpu.icache.demand_misses 10060 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 353 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 31759000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10060 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 19216915 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5291.898608 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 18006143 # number of overall hits
-system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10122 # number of overall misses
-system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses
+system.cpu.icache.overall_hits 19206855 # number of overall hits
+system.cpu.icache.overall_miss_latency 53236500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses
+system.cpu.icache.overall_misses 10060 # number of overall misses
+system.cpu.icache.overall_mshr_hits 353 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 31759000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10060 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,162 +217,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 7904 # number of replacements
-system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8146 # number of replacements
+system.cpu.icache.sampled_refs 10060 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use
-system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1551.624399 # Cycle average of tags in use
+system.cpu.icache.total_refs 19206855 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12543861 # Number of branches executed
-system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate
-system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7145648 # Number of stores executed
+system.cpu.idleCycles 435727 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12761226 # Number of branches executed
+system.cpu.iew.EXEC:nop 12552336 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.247935 # Inst execution rate
+system.cpu.iew.EXEC:refs 31899012 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7188094 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value
-system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back
+system.cpu.iew.WB:consumers 90808493 # num instructions consuming a value
+system.cpu.iew.WB:count 99646578 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.722903 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 63859133 # num instructions producing a value
-system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle
-system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 65645732 # num instructions producing a value
+system.cpu.iew.WB:rate 1.224322 # insts written-back per cycle
+system.cpu.iew.WB:sent 100573545 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2105709 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 285403 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 33916617 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1714541 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 10592327 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 147619094 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24710918 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2203361 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 101568426 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 132795 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8016661 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 165683 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 838013 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 1487 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 249026 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 13882204 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4089632 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 249026 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 202527 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1903182 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.034286 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.034286 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 103771787 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 7 0.00% # Type of FU issued
- IntAlu 62609480 61.69% # Type of FU issued
- IntMult 467679 0.46% # Type of FU issued
+ No_OpClass 7 0.00% # Type of FU issued
+ IntAlu 64228940 61.89% # Type of FU issued
+ IntMult 473017 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2780950 2.74% # Type of FU issued
- FloatCmp 115557 0.11% # Type of FU issued
- FloatCvt 2364134 2.33% # Type of FU issued
- FloatMult 305451 0.30% # Type of FU issued
- FloatDiv 755050 0.74% # Type of FU issued
- FloatSqrt 320 0.00% # Type of FU issued
- MemRead 24826231 24.46% # Type of FU issued
- MemWrite 7259828 7.15% # Type of FU issued
+ FloatAdd 2790055 2.69% # Type of FU issued
+ FloatCmp 115633 0.11% # Type of FU issued
+ FloatCvt 2376207 2.29% # Type of FU issued
+ FloatMult 305676 0.29% # Type of FU issued
+ FloatDiv 755062 0.73% # Type of FU issued
+ FloatSqrt 323 0.00% # Type of FU issued
+ MemRead 25409003 24.49% # Type of FU issued
+ MemWrite 7317864 7.05% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1978136 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019062 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 236478 13.59% # attempts to use FU when none available
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 311313 15.74% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 1 0.00% # attempts to use FU when none available
+ FloatAdd 546 0.03% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 223 0.01% # attempts to use FU when none available
- FloatMult 1629 0.09% # attempts to use FU when none available
- FloatDiv 705159 40.54% # attempts to use FU when none available
+ FloatCvt 3483 0.18% # attempts to use FU when none available
+ FloatMult 2460 0.12% # attempts to use FU when none available
+ FloatDiv 833660 42.14% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 710061 40.82% # attempts to use FU when none available
- MemWrite 85961 4.94% # attempts to use FU when none available
+ MemRead 753551 38.09% # attempts to use FU when none available
+ MemWrite 73123 3.70% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924
+system.cpu.iq.ISSUE:issued_per_cycle.samples 81389202
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 43673541 4933.25%
- 1 18286123 2065.55%
- 2 11155754 1260.13%
- 3 6962814 786.50%
- 4 4628513 522.82%
- 5 2073707 234.24%
- 6 1255435 141.81%
- 7 360879 40.76%
- 8 132158 14.93%
+ 0 35308856 4338.27%
+ 1 18677963 2294.89%
+ 2 11652538 1431.71%
+ 3 6999702 860.03%
+ 4 4887440 600.50%
+ 5 2229546 273.94%
+ 6 1377818 169.29%
+ 7 217468 26.72%
+ 8 37871 4.65%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate
-system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
+system.cpu.iq.ISSUE:rate 1.275007 # Inst issue rate
+system.cpu.iq.iqInstsAdded 135066329 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 103771787 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 50270340 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 231965 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 47066497 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 1741 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4485.353245 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2485.353245 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 7809000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1741 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4327000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1741 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 10559 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4274.193548 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2274.193548 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7149 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14575000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.322947 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 7755000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322947 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 118 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 531000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 118 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 295000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 118 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 106 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 106 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.172948 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12300 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4345.563968 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7149 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 22384000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.418780 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5151 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 12082000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.418780 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5151 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 12300 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4345.563968 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7082 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5088 # number of overall misses
+system.cpu.l2cache.overall_hits 7149 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 22384000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.418780 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5151 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 12082000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.418780 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -383,30 +406,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3290 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2252.890734 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7149 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 88528924 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking
+system.cpu.numCycles 81389202 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 1683934 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed
-system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 1032549 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 40751116 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 970163 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 202965992 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 157380306 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 115963922 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 28805465 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8016661 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2127274 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 47536561 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 4752 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4689522 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed
+system.cpu.timesIdled 283 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 7edcc9166..56cac7865 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
@@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index 9f5824722..1f35acc4a 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 651405 # Simulator instruction rate (inst/s)
-host_mem_usage 156232 # Number of bytes of host memory used
-host_seconds 141.08 # Real time elapsed on the host
-host_tick_rate 840119018 # Simulator tick rate (ticks/s)
+host_inst_rate 1713530 # Simulator instruction rate (inst/s)
+host_mem_usage 204416 # Number of bytes of host memory used
+host_seconds 53.63 # Real time elapsed on the host
+host_tick_rate 2211088665 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated
-sim_seconds 0.118528 # Number of seconds simulated
-sim_ticks 118527938000 # Number of ticks simulated
+sim_seconds 0.118590 # Number of seconds simulated
+sim_ticks 118589598000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 11526000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 10578000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 46475000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 42757000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 24861.123018 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 58001000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 53335000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24861.123018 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26495079 # number of overall hits
-system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2222 # number of overall misses
+system.cpu.dcache.overall_hits 26494968 # number of overall hits
+system.cpu.dcache.overall_miss_latency 58001000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2333 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 53335000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.457790 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 125062000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 125062000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 91894548 # number of overall hits
-system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 125062000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1418.474486 # Cycle average of tags in use
system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 38456000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 5916 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 67496000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.341496 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3068 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 33748000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.341496 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3068 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2442000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 104 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 104 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.002030 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 5916 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 105952000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.448751 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4816 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 52976000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.448751 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4816 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 6072 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4764 # number of overall misses
+system.cpu.l2cache.overall_hits 5916 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 105952000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.448751 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4816 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 52976000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.448751 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4816 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -201,14 +222,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2014.752255 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 118527938000 # number of cpu cycles simulated
+system.cpu.numCycles 118589598000 # number of cpu cycles simulated
system.cpu.num_insts 91903057 # Number of instructions executed
system.cpu.num_refs 26537109 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls