diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
| commit | d1dd7a24dbeec44a5de232549fa863ff597be349 (patch) | |
| tree | 83755e42e7507fd86f6f573d13570118dec9549e /tests/long/70.twolf/ref/arm | |
| parent | 61c14da751ae80e8c19e0b63ddd629c4152f1c72 (diff) | |
| download | gem5-d1dd7a24dbeec44a5de232549fa863ff597be349.tar.xz | |
imported patch ext/stats_updates.patch
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
Diffstat (limited to 'tests/long/70.twolf/ref/arm')
| -rw-r--r-- | tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 742 |
3 files changed, 376 insertions, 378 deletions
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 342457a8b..e5f29e92c 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 7a94cf61c..e68aac2cc 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 18:53:02 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -25,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105782426500 because target called exit() +122 123 124 Exiting @ tick 105874925000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9c02493cb..37554b8e7 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105782 # Number of seconds simulated -sim_ticks 105782426500 # Number of ticks simulated +sim_seconds 0.105875 # Number of seconds simulated +sim_ticks 105874925000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104930 # Simulator instruction rate (inst/s) -host_tick_rate 58832155 # Simulator tick rate (ticks/s) -host_mem_usage 220996 # Number of bytes of host memory used -host_seconds 1798.04 # Real time elapsed on the host -sim_insts 188667447 # Number of instructions simulated +host_inst_rate 114442 # Simulator instruction rate (inst/s) +host_tick_rate 64221605 # Simulator tick rate (ticks/s) +host_mem_usage 218340 # Number of bytes of host memory used +host_seconds 1648.59 # Real time elapsed on the host +sim_insts 188667572 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211564854 # number of cpu cycles simulated +system.cpu.numCycles 211749851 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102102959 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80693522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9934423 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84198795 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79209656 # Number of BTB hits +system.cpu.BPredUnit.lookups 102127285 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80698368 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9933568 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84243150 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79257318 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4697254 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 112889 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44543100 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416703604 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102102959 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83906910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108778714 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33211132 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 34936553 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 779 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4698618 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 111511 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44551125 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 416786863 # Number of instructions fetch has processed +system.cpu.fetch.Branches 102127285 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83955936 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 108810185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 33218375 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35074253 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40617038 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2208646 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211506610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137206 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 40624886 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2204416 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 211691341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.135529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102929819 48.67% 48.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4598020 2.17% 50.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32955527 15.58% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18221421 8.62% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9181259 4.34% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12523238 5.92% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8470282 4.00% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4319419 2.04% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18307625 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 103083318 48.70% 48.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4611723 2.18% 50.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32955553 15.57% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18242297 8.62% 75.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9176940 4.34% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12529739 5.92% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8472403 4.00% 89.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4322449 2.04% 91.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18296919 8.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211506610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482608 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.969626 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53228641 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33488153 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100485702 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1214398 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23089716 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14176819 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166958 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422710144 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 694356 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23089716 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62181422 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455271 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28556828 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92670031 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4553342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388732639 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2224138 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666278753 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1657677699 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1639787081 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17890618 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061648 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368217100 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2705646 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2657641 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23338281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46771972 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16999423 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3794588 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2434419 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332719440 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2206649 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261972515 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1005249 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143535623 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342170938 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 571067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211506610 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.491475 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 211691341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.482302 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.968298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53244805 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 33622636 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 100506105 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1219607 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23098188 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14186059 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166456 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 422686981 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 695509 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23098188 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62205667 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 461892 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28663713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 92688664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4573217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 388586256 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22473 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2248529 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 666261253 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1656600047 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1638859233 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17740814 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061848 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 368199405 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2723713 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2675909 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23519864 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 46897665 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16902365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3883401 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2525721 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332696460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2225712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261853052 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 956132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 143515224 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 342118821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 589705 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 211691341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.236957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.489139 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97729672 46.21% 46.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37811383 17.88% 64.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34093128 16.12% 80.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22769109 10.77% 90.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11443716 5.41% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4778532 2.26% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2323194 1.10% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 402147 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 155729 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 97854722 46.23% 46.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37874169 17.89% 64.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34110087 16.11% 80.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22786114 10.76% 90.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11453676 5.41% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4761165 2.25% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2318956 1.10% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 393514 0.19% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138938 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211506610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 211691341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397392 17.88% 17.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5524 0.25% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 43 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1333839 60.01% 78.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 485736 21.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 398184 18.25% 18.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1324595 60.71% 79.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453293 20.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 205005652 78.25% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928362 0.35% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 5862 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33106 0.01% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166621 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 256879 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76399 0.03% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467584 0.18% 78.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207638 0.08% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71818 0.03% 79.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 328 0.00% 79.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40692198 15.53% 94.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14060068 5.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 204944335 78.27% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928862 0.35% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166569 0.06% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 257495 0.10% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76397 0.03% 78.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 468208 0.18% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207568 0.08% 79.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71821 0.03% 79.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 40739224 15.56% 94.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13959176 5.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261972515 # Type of FU issued -system.cpu.iq.rate 1.238261 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2222588 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008484 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734922033 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476231649 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242866615 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3757444 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2242269 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844486 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262305042 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1890061 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261853052 # Type of FU issued +system.cpu.iq.rate 1.236615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2181696 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 734785745 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 476212492 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242882419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3749528 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2237188 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1845400 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262148601 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1886147 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1588917 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16920299 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31179 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12638 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4352602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17045968 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31330 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12732 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4255519 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 19 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23089716 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13717 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1061 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334979671 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3743340 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46771972 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16999423 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2182801 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23098188 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 833 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334975630 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3751995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 46897665 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16902365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2201836 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 328 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12638 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9998550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1696549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11695099 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249247765 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38548373 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12724750 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12732 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9997150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1695546 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11692696 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 249230612 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 38607191 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12622440 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53582 # number of nop insts executed -system.cpu.iew.exec_refs 52189835 # number of memory reference insts executed -system.cpu.iew.exec_branches 52589546 # Number of branches executed -system.cpu.iew.exec_stores 13641462 # Number of stores executed -system.cpu.iew.exec_rate 1.178115 # Inst execution rate -system.cpu.iew.wb_sent 246271273 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244711101 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148454614 # num instructions producing a value -system.cpu.iew.wb_consumers 247957784 # num instructions consuming a value +system.cpu.iew.exec_nop 53458 # number of nop insts executed +system.cpu.iew.exec_refs 52205543 # number of memory reference insts executed +system.cpu.iew.exec_branches 52589382 # Number of branches executed +system.cpu.iew.exec_stores 13598352 # Number of stores executed +system.cpu.iew.exec_rate 1.177005 # Inst execution rate +system.cpu.iew.wb_sent 246260336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 244727819 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148531018 # num instructions producing a value +system.cpu.iew.wb_consumers 247826872 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.156672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598709 # average fanout of values written-back +system.cpu.iew.wb_rate 1.155740 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.599334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188681835 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146288700 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635582 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9795726 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188416895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.001406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.682967 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681960 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146293697 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636007 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9795278 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 188593154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.000471 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.681076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105298145 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40798709 21.65% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19462081 10.33% 87.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8761911 4.65% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4909468 2.61% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2009419 1.07% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1710426 0.91% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008180 0.54% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4458556 2.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 105401505 55.89% 55.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 40855723 21.66% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19482895 10.33% 87.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8763575 4.65% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4920568 2.61% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2013461 1.07% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1707502 0.91% 97.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008267 0.53% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4439658 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188416895 # Number of insts commited each cycle -system.cpu.commit.count 188681835 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 188593154 # Number of insts commited each cycle +system.cpu.commit.count 188681960 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498493 # Number of memory references committed -system.cpu.commit.loads 29851672 # Number of loads committed +system.cpu.commit.refs 42498543 # Number of memory references committed +system.cpu.commit.loads 29851697 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283870 # Number of branches committed +system.cpu.commit.branches 40283895 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150114973 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115073 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4458556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4439658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 518923673 # The number of ROB reads -system.cpu.rob.rob_writes 693093847 # The number of ROB writes -system.cpu.timesIdled 1715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667447 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667447 # Number of Instructions Simulated -system.cpu.cpi 1.121364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.121364 # CPI: Total CPI of All Threads -system.cpu.ipc 0.891771 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.891771 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1112037925 # number of integer regfile reads -system.cpu.int_regfile_writes 407325224 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928951 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497682 # number of floating regfile writes -system.cpu.misc_regfile_reads 502867512 # number of misc regfile reads -system.cpu.misc_regfile_writes 824410 # number of misc regfile writes -system.cpu.icache.replacements 1940 # number of replacements -system.cpu.icache.tagsinuse 1334.073699 # Cycle average of tags in use -system.cpu.icache.total_refs 40612809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3646 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11139.004114 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 519123952 # The number of ROB reads +system.cpu.rob.rob_writes 693113124 # The number of ROB writes +system.cpu.timesIdled 1721 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58510 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667572 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667572 # Number of Instructions Simulated +system.cpu.cpi 1.122344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.122344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.890993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.890993 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1112090730 # number of integer regfile reads +system.cpu.int_regfile_writes 407417013 # number of integer regfile writes +system.cpu.fp_regfile_reads 2928432 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499453 # number of floating regfile writes +system.cpu.misc_regfile_reads 503028333 # number of misc regfile reads +system.cpu.misc_regfile_writes 824460 # number of misc regfile writes +system.cpu.icache.replacements 1929 # number of replacements +system.cpu.icache.tagsinuse 1329.893683 # Cycle average of tags in use +system.cpu.icache.total_refs 40620654 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3638 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11165.655305 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1334.073699 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.651403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 40612809 # number of ReadReq hits -system.cpu.icache.demand_hits 40612809 # number of demand (read+write) hits -system.cpu.icache.overall_hits 40612809 # number of overall hits -system.cpu.icache.ReadReq_misses 4229 # number of ReadReq misses -system.cpu.icache.demand_misses 4229 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101377500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101377500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101377500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 40617038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 40617038 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 40617038 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1329.893683 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.649362 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 40620654 # number of ReadReq hits +system.cpu.icache.demand_hits 40620654 # number of demand (read+write) hits +system.cpu.icache.overall_hits 40620654 # number of overall hits +system.cpu.icache.ReadReq_misses 4232 # number of ReadReq misses +system.cpu.icache.demand_misses 4232 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 40624886 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 40624886 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 40624886 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23971.979191 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23971.979191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23971.979191 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 23946.951796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23946.951796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23946.951796 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,139 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3646 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3646 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3646 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3638 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74805000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74666000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20517.004937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20523.914239 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1408.142162 # Cycle average of tags in use -system.cpu.dcache.total_refs 48578921 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1851 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26244.689897 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1403.749083 # Cycle average of tags in use +system.cpu.dcache.total_refs 48644661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1849 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 26308.632234 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.142162 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343785 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36170054 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356741 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27532 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 48526795 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 48526795 # number of overall hits -system.cpu.dcache.ReadReq_misses 1787 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7546 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1403.749083 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.342712 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 36235521 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356728 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27793 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24619 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 48592249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 48592249 # number of overall hits +system.cpu.dcache.ReadReq_misses 1802 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7559 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9333 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9333 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59024500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236727000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59198500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 237194000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 295751500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 295751500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36171841 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 296392500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296392500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 36237323 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27534 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24594 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 48536128 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 48536128 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000073 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33029.938444 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31371.190034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 27795 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24619 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 48601610 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 48601610 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32851.553829 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31379.018389 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31688.792457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31688.792457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31662.482641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31662.482641 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1026 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1044 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6468 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7482 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7482 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1851 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7512 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7512 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 758 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1849 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1849 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24308000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62630000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62630000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62497000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62497000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.181340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35157.798165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31864.116095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1934.153388 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2689 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.637412 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1924.111202 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2681 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.638195 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1931.095297 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.058091 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 1920.073953 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 4.037248 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058596 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000123 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 19 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3774 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129478000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 1720 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1720 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2685 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3767 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3767 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92055500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37184500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129240000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 19 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1090 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5497 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5497 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.611073 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991743 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.686556 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.686556 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34279.985147 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34377.428307 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34307.896131 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34307.896131 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5487 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5487 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.610783 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.686532 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.686532 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34285.102421 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.451017 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34308.468277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34308.468277 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,24 +498,24 @@ system.cpu.l2cache.writebacks 0 # nu system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2679 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3760 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3760 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 2671 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3753 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83267000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33562000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116829000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116829000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83018000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116608000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116608000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607897 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.684009 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.684009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.373647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31047.178538 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607598 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.683980 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.683980 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.242980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |