diff options
author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/long/70.twolf/ref/sparc/linux/simple-timing | |
parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/long/70.twolf/ref/sparc/linux/simple-timing')
4 files changed, 70 insertions, 70 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index a7e0f9783..cf8698574 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 6a57afc45..40cd826e7 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1517830 # Simulator instruction rate (inst/s) -host_mem_usage 218636 # Number of bytes of host memory used -host_seconds 127.45 # Real time elapsed on the host -host_tick_rate 2121861871 # Simulator tick rate (ticks/s) +host_inst_rate 1409829 # Simulator instruction rate (inst/s) +host_mem_usage 207084 # Number of bytes of host memory used +host_seconds 137.21 # Real time elapsed on the host +host_tick_rate 1971980655 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270428 # Number of seconds simulated -sim_ticks 270428013000 # Number of ticks simulated +sim_seconds 0.270579 # Number of seconds simulated +sim_ticks 270578958000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 29916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 26592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43362000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 89936000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 38544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 85118000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76709902 # number of overall hits -system.cpu.dcache.overall_miss_latency 43362000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 89936000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1606 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 38544000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 85118000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1235.387438 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1235.200907 # Cycle average of tags in use system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 17805.419922 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 14805.419922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 218793000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 181929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 17805.419922 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 218793000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 181929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 17805.419922 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193433499 # number of overall hits -system.cpu.icache.overall_miss_latency 218793000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses system.cpu.icache.overall_misses 12288 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 181929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.780933 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.567399 # Cycle average of tags in use system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 24955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 56420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 11935000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94185000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 45045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 119140000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 269360000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 56980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 207200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.overall_miss_latency 119140000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 269360000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5180 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 56980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 207200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.731325 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.336317 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 540856026 # number of cpu cycles simulated +system.cpu.numCycles 541157916 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index d6124e8ba..047da0c93 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index bac654c3b..88fe50099 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 23 2008 16:00:51 -M5 started Wed Jul 23 16:02:07 2008 -M5 executing on blue -M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf -M5 commit date Wed Jul 23 15:35:08 2008 -0700 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:29:26 2008 +M5 executing on zizzer +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 @@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 270428013000 because target called exit() +122 123 124 Exiting @ tick 270578958000 because target called exit() |