tests: update stats for name changes

5 files changed, 23 insertions, 22 deletions

diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index f4dfd8899..9f7fb86bc 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:39
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:03
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 5f3549812..df028f09a 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1142521                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224208                       # Number of bytes of host memory used
-host_seconds                                   169.31                       # Real time elapsed on the host
-host_tick_rate                              571263026                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4299467                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202100                       # Number of bytes of host memory used
+host_seconds                                    44.99                       # Real time elapsed on the host
+host_tick_rate                             2149737482                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          163703467                       # nu
 system.cpu.num_load_insts                    57735092                       # Number of load instructions
 system.cpu.num_mem_refs                      76733959                       # number of memory refs
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index c8439f7fb..1787724e4 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index a4abb12dd..748c08434 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:19
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:39
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index f02c69451..9ba399fb8 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 498703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231920                       # Number of bytes of host memory used
-host_seconds                                   387.90                       # Real time elapsed on the host
-host_tick_rate                              697549821                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2425845                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209848                       # Number of bytes of host memory used
+host_seconds                                    79.74                       # Real time elapsed on the host
+host_tick_rate                             3393094719                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270577                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses             1575                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.302050                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1237.197455                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.302050                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           76711508                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses            12288                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.777135                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1591.571713                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.777135                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
@@ -182,10 +182,10 @@ system.cpu.l2cache.demand_mshr_misses            5173                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.081736                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2678.326682                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             0.000454                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             13864                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -227,6 +227,6 @@ system.cpu.num_int_register_writes          163703466                       # nu
 system.cpu.num_load_insts                    57735092                       # Number of load instructions
 system.cpu.num_mem_refs                      76733959                       # number of memory refs
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------