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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
commit0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch)
tree96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/70.twolf/ref/sparc
parent1b64bfa933745294667158d0ce22180780b2a22e (diff)
downloadgem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz
Stats: Re update stats.
Diffstat (limited to 'tests/long/70.twolf/ref/sparc')
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-atomic/simout10
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt26
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini13
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-timing/simout16
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt26
6 files changed, 77 insertions, 27 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 1b0da48ab..c1dd735f6 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@@ -57,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index 30e9edddf..f4dfd8899 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:35:37
-M5 executing on SC2B0619
+M5 compiled Feb 7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 02:13:39
+M5 executing on burrito
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index ec86f0831..5f3549812 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1979245 # Simulator instruction rate (inst/s)
-host_mem_usage 190260 # Number of bytes of host memory used
-host_seconds 97.74 # Real time elapsed on the host
-host_tick_rate 989625806 # Simulator tick rate (ticks/s)
+host_inst_rate 1142521 # Simulator instruction rate (inst/s)
+host_mem_usage 224208 # Number of bytes of host memory used
+host_seconds 169.31 # Real time elapsed on the host
+host_tick_rate 571263026 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.096723 # Number of seconds simulated
@@ -11,8 +11,24 @@ sim_ticks 96722951500 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 193445904 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 193445904 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
+system.cpu.num_fp_insts 1970372 # number of float instructions
+system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 193444769 # Number of instructions executed
-system.cpu.num_refs 76733959 # Number of memory references
+system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
+system.cpu.num_int_insts 167974818 # number of integer instructions
+system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read
+system.cpu.num_int_register_writes 163703467 # number of times the integer registers were written
+system.cpu.num_load_insts 57735092 # Number of load instructions
+system.cpu.num_mem_refs 76733959 # number of memory refs
+system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index dc0731aa6..c8439f7fb 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -152,7 +161,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index a4fbf8115..a4abb12dd 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:03:51
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+M5 compiled Feb 7 2011 02:13:30
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 02:14:19
+M5 executing on burrito
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 46f688248..f02c69451 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 953366 # Simulator instruction rate (inst/s)
-host_mem_usage 216056 # Number of bytes of host memory used
-host_seconds 202.91 # Real time elapsed on the host
-host_tick_rate 1333500122 # Simulator tick rate (ticks/s)
+host_inst_rate 498703 # Simulator instruction rate (inst/s)
+host_mem_usage 231920 # Number of bytes of host memory used
+host_seconds 387.90 # Real time elapsed on the host
+host_tick_rate 697549821 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.270577 # Number of seconds simulated
@@ -209,8 +209,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 541153920 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 541153920 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
+system.cpu.num_fp_insts 1970372 # number of float instructions
+system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 193444769 # Number of instructions executed
-system.cpu.num_refs 76733959 # Number of memory references
+system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
+system.cpu.num_int_insts 167974818 # number of integer instructions
+system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read
+system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written
+system.cpu.num_load_insts 57735092 # Number of load instructions
+system.cpu.num_mem_refs 76733959 # number of memory refs
+system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
---------- End Simulation Statistics ----------