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authorGabe Black <gblack@eecs.umich.edu>2008-02-26 02:20:40 -0500
committerGabe Black <gblack@eecs.umich.edu>2008-02-26 02:20:40 -0500
commit8833b4cd44457d50b45a4dfe642cdb5e51c0889d (patch)
tree64417a9e2d759dc367848de4b7ee117b3903dc54 /tests/long/70.twolf/ref/sparc
parentec1a4cbbc73ecc1d7456d11c571c425e226a7d3b (diff)
downloadgem5-8833b4cd44457d50b45a4dfe642cdb5e51c0889d.tar.xz
Bus: Update the stats for the recent bus fix.
--HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Diffstat (limited to 'tests/long/70.twolf/ref/sparc')
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt104
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout12
4 files changed, 62 insertions, 58 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 62ae5d2bf..fe6c893b2 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -152,6 +152,7 @@ type=Bus
block_size=64
bus_id=0
clock=1000
+header_cycles=1
responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -181,6 +182,7 @@ type=Bus
block_size=64
bus_id=0
clock=1000
+header_cycles=1
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.l2cache.mem_side
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
index 1a1f8243f..b8ccd7e90 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 615476 # Simulator instruction rate (inst/s)
-host_mem_usage 157048 # Number of bytes of host memory used
-host_seconds 314.29 # Real time elapsed on the host
-host_tick_rate 860356799 # Simulator tick rate (ticks/s)
+host_inst_rate 1067073 # Simulator instruction rate (inst/s)
+host_mem_usage 203488 # Number of bytes of host memory used
+host_seconds 181.28 # Real time elapsed on the host
+host_tick_rate 1491737734 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435005 # Number of instructions simulated
-sim_seconds 0.270398 # Number of seconds simulated
-sim_ticks 270397899000 # Number of ticks simulated
+sim_seconds 0.270417 # Number of seconds simulated
+sim_ticks 270416976000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12450000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 11454000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 27750000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 29970000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 25530000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 26640000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 40200000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 43416000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 36984000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 38592000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 76708944 # number of overall hits
-system.cpu.dcache.overall_miss_latency 40200000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 43416000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1608 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 36984000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 38592000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 26 # number of replacements
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1237.402352 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1237.389513 # Cycle average of tags in use
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 23 # number of writebacks
system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 17803.146397 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 14803.146397 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 218409000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 178016000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 181605000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 17803.146397 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency
system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 218409000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 178016000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 181605000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 17803.146397 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 193423750 # number of overall hits
-system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 218409000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.overall_misses 12268 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 178016000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 181605000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 10342 # number of replacements
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1591.726789 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1591.711897 # Cycle average of tags in use
system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 23914000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 25001000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 89914000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 94001000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 550000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles
@@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 113828000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 119002000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 8679 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 113828000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 119002000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5174 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2649.709095 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2649.681897 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 540795798 # number of cpu cycles simulated
+system.cpu.numCycles 540833952 # number of cpu cycles simulated
system.cpu.num_insts 193435005 # Number of instructions executed
system.cpu.num_refs 76733003 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
index 5992f7131..d6124e8ba 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7005
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index bc5990f1f..0d7eb187f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -13,14 +13,16 @@ Authors: Carl Sechen, Bill Swartz
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 M5 Simulator System
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 13 2008 00:33:29
-M5 started Wed Feb 13 18:42:03 2008
-M5 executing on zizzer
+M5 compiled Feb 24 2008 13:27:50
+M5 started Mon Feb 25 16:18:16 2008
+M5 executing on tater
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 270397899000 because target called exit()
+Exiting @ tick 270416976000 because target called exit()