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authorSteve Reinhardt <stever@gmail.com>2008-02-16 14:58:37 -0500
committerSteve Reinhardt <stever@gmail.com>2008-02-16 14:58:37 -0500
commit3204f968091d32846a59c0666157c6c8946842d1 (patch)
tree497c84fa2634b7bcd6c0a5ab03e6d602c264fd07 /tests/long/70.twolf/ref/sparc
parent4597a71cef808969c442fca73ae662efe75550d7 (diff)
downloadgem5-3204f968091d32846a59c0666157c6c8946842d1.tar.xz
Update stats for new writeback behavior.
--HG-- extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
Diffstat (limited to 'tests/long/70.twolf/ref/sparc')
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt19
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout6
3 files changed, 12 insertions, 15 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
index 11499dff9..1a1f8243f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1710803 # Simulator instruction rate (inst/s)
-host_mem_usage 188480 # Number of bytes of host memory used
-host_seconds 113.07 # Real time elapsed on the host
-host_tick_rate 2391482744 # Simulator tick rate (ticks/s)
+host_inst_rate 615476 # Simulator instruction rate (inst/s)
+host_mem_usage 157048 # Number of bytes of host memory used
+host_seconds 314.29 # Real time elapsed on the host
+host_tick_rate 860356799 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435005 # Number of instructions simulated
sim_seconds 0.270398 # Number of seconds simulated
@@ -182,13 +182,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 23 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 23 # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.136632 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.128249 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@@ -232,9 +229,9 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2649.703495 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2649.709095 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
index 2fe6268cd..5992f7131 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7010
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index 45fe06809..bc5990f1f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -18,9 +18,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
+M5 compiled Feb 13 2008 00:33:29
+M5 started Wed Feb 13 18:42:03 2008
+M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 270397899000 because target called exit()