diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-12 21:35:03 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-12 21:35:03 -0400 |
| commit | 1aa4869ff046d0a039f132de49c8cfe28a6566cf (patch) | |
| tree | 2523e4e0a795f08bdf506445ff2bf58d2b132544 /tests/long/70.twolf/ref/sparc | |
| parent | fb8c95824144d1984539f7a918086f87858ff27d (diff) | |
| download | gem5-1aa4869ff046d0a039f132de49c8cfe28a6566cf.tar.xz | |
sparc: update long regressions
Diffstat (limited to 'tests/long/70.twolf/ref/sparc')
8 files changed, 241 insertions, 247 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index c1dd735f6..ee5b3b672 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 9f7fb86bc..705894fd8 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:20:03 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +gem5 compiled Jun 12 2011 07:14:44 +gem5 started Jun 12 2011 07:14:52 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index df028f09a..c1047d2b2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4299467 # Simulator instruction rate (inst/s) -host_mem_usage 202100 # Number of bytes of host memory used -host_seconds 44.99 # Real time elapsed on the host -host_tick_rate 2149737482 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated sim_ticks 96722951500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2494224 # Simulator instruction rate (inst/s) +host_tick_rate 1247118942 # Simulator tick rate (ticks/s) +host_mem_usage 225000 # Number of bytes of host memory used +host_seconds 77.56 # Real time elapsed on the host +sim_insts 193444769 # Number of instructions simulated +system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445904 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 193445904 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read system.cpu.num_int_register_writes 163703467 # number of times the integer registers were written -system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 193445904 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 1787724e4..89315cddc 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -164,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 748c08434..d8ad09e2a 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:21:39 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +gem5 compiled Jun 12 2011 07:14:44 +gem5 started Jun 12 2011 07:16:32 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 9ba399fb8..03f17b992 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,232 +1,232 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2425845 # Simulator instruction rate (inst/s) -host_mem_usage 209848 # Number of bytes of host memory used -host_seconds 79.74 # Real time elapsed on the host -host_tick_rate 3393094719 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270577 # Number of seconds simulated sim_ticks 270576960000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1189238 # Simulator instruction rate (inst/s) +host_tick_rate 1663421950 # Simulator tick rate (ticks/s) +host_mem_usage 233652 # Number of bytes of host memory used +host_seconds 162.66 # Real time elapsed on the host +sim_insts 193444769 # Number of instructions simulated +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 541153920 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read +system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 541153920 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 10362 # number of replacements +system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use +system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits +system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits +system.cpu.icache.overall_hits 193433261 # number of overall hits +system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses +system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses +system.cpu.icache.overall_misses 12288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2 # number of replacements +system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 76709933 # number of overall hits +system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits +system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses +system.cpu.dcache.writebacks 2 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76709933 # number of overall hits -system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1575 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses -system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193433261 # number of overall hits -system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses -system.cpu.icache.overall_misses 12288 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use -system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 8691 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5173 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5173 # number of overall misses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541153920 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 541153920 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses -system.cpu.num_int_insts 167974818 # number of integer instructions -system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read -system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written -system.cpu.num_load_insts 57735092 # Number of load instructions -system.cpu.num_mem_refs 76733959 # number of memory refs -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |