update all the regresstion tests for release

--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2

8 files changed, 75 insertions, 75 deletions

diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 5aa5f86fe..3dcf027c2 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -48,6 +48,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
index f078d661c..d448056f4 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
index 5532c6dba..c41d3b35f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 668374                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 150556                       # Number of bytes of host memory used
-host_seconds                                   289.41                       # Real time elapsed on the host
-host_tick_rate                              334186387                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 673586                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 150548                       # Number of bytes of host memory used
+host_seconds                                   287.17                       # Real time elapsed on the host
+host_tick_rate                              336792536                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193435973                       # Number of instructions simulated
 sim_seconds                                  0.096718                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
index 2cdcc205c..f878587c3 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -18,8 +18,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 16:03:50 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 16:48:51 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index ec76ab996..2a87cb78d 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -75,8 +74,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -114,8 +112,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
@@ -171,6 +169,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
index dbecb5fa5..f79151c21 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
@@ -61,13 +62,14 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.icache]
 type=BaseCache
 size=131072
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -98,14 +100,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.dcache]
 type=BaseCache
 size=262144
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -136,14 +137,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.l2cache]
 type=BaseCache
 size=2097152
 assoc=2
 block_size=64
-latency=1
+latency=10000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -174,5 +174,4 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
index 2c6679b72..0f4d2b473 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 490451                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 156012                       # Number of bytes of host memory used
-host_seconds                                   394.40                       # Real time elapsed on the host
-host_tick_rate                              342594746                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 500598                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156000                       # Number of bytes of host memory used
+host_seconds                                   386.41                       # Real time elapsed on the host
+host_tick_rate                              699597163                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193435973                       # Number of instructions simulated
-sim_seconds                                  0.135121                       # Number of seconds simulated
-sim_ticks                                135120940500                       # Number of ticks simulated
+sim_seconds                                  0.270332                       # Number of seconds simulated
+sim_ticks                                270331639000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           57734138                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3786.144578                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2786.144578                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency        14000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        13000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               57733640                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        1885500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        6972000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  498                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1387500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      6474000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             498                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses              22406                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency         3500                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency         2500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        14000                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        13000                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_hits                  22405                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency           3500                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency          14000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_rate          0.000045                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_misses                    1                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency         2500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency        13000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.000045                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses               1                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          18976414                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3587.016575                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2587.016575                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              18975328                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       3895500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      15190000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000057                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                1086                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      2809500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     14104000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000057                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           1086                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            76710552                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3649.621212                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2649.621212                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 13991.161616                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                76708968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         5781000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency        22162000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000021                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                  1584                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      4197000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     20578000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000021                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses             1584                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           76710552                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3649.621212                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2649.621212                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 13991.161616                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               76708968                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        5781000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency       22162000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000021                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                 1584                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      4197000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     20578000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000021                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            1584                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                     26                       # number of replacements
 system.cpu.dcache.sampled_refs                   1585                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1237.515646                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1237.473868                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 76731373                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                       23                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          193435974                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3066.269971                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2066.269971                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 12584.365830                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              193423706                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       37617000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      154385000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000063                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                12268                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     25349000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    142117000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000063                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           12268                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           193435974                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3066.269971                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2066.269971                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 12584.365830                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               193423706                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        37617000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       154385000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000063                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 12268                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25349000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    142117000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000063                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            12268                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          193435974                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3066.269971                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2066.269971                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 12584.365830                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              193423706                       # number of overall hits
-system.cpu.icache.overall_miss_latency       37617000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      154385000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000063                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                12268                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25349000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    142117000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000063                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           12268                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                  10342                       # number of replacements
 system.cpu.icache.sampled_refs                  12268                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1591.858190                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1591.809550                       # Cycle average of tags in use
 system.cpu.icache.total_refs                193423706                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses             13852                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2720.824463                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1719.824463                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  8685                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      14058500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      67171000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.373015                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                5167                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      8886333                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     56837000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.373015                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           5167                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses              23                       # number of Writeback accesses(hits+misses)
@@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses              13852                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2720.824463                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1719.824463                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                   8685                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       14058500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency       67171000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.373015                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 5167                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency      8886333                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     56837000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.373015                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses            5167                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses             13875                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2720.824463                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1719.824463                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                  8708                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      14058500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency      67171000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.372396                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                5167                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      8886333                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     56837000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.372396                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses           5167                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  5167                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3507.285738                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3507.169610                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    8708                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     135120940500                       # number of cpu cycles simulated
+system.cpu.numCycles                     270331639000                       # number of cpu cycles simulated
 system.cpu.num_insts                        193435973                       # Number of instructions executed
 system.cpu.num_refs                          76732959                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             396                       # Number of system calls
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index eb4e3bbfa..316a2c0d3 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -18,11 +18,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 16:08:41 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 16:53:38 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 135120940500 because target called exit()
+Exiting @ tick 270331639000 because target called exit()