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author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:18:45 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:18:45 -0800 |
commit | 1bfab291f1899a3e241977425339c799dc96fa9d (patch) | |
tree | 5ce83cb49bca9aea30550505099f8e59e2082d28 /tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | |
parent | da61c4b3ee4571d43f7133640eeda2cf51e21cd9 (diff) | |
download | gem5-1bfab291f1899a3e241977425339c799dc96fa9d.tar.xz |
CPU: Update stats now that there's no fetch in the middle of macroops.
Diffstat (limited to 'tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a85a5c18f..3d7cbb069 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 565225 # Simulator instruction rate (inst/s) -host_mem_usage 211860 # Number of bytes of host memory used -host_seconds 386.74 # Real time elapsed on the host -host_tick_rate 872598896 # Simulator tick rate (ticks/s) +host_inst_rate 660588 # Simulator instruction rate (inst/s) +host_mem_usage 211972 # Number of bytes of host memory used +host_seconds 330.91 # Real time elapsed on the host +host_tick_rate 758349031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated -sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469588000 # Number of ticks simulated +sim_seconds 0.250945 # Number of seconds simulated +sim_ticks 250945484000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits +system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013777 # number of overall hits +system.cpu.icache.overall_hits 173489673 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use -system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use +system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939176 # number of cpu cycles simulated +system.cpu.numCycles 501890968 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |