stats: update stats for the changes I pushed re: shared cache occupancy

6 files changed, 31 insertions, 20 deletions

diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 4d458b23f..77f906a7d 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -52,12 +52,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 1b109ceb4..d0e32b9a8 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:37:58
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:02:03
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index d9b5a344c..556a9fb7a 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 608858                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 220444                       # Number of bytes of host memory used
-host_seconds                                   360.40                       # Real time elapsed on the host
-host_tick_rate                              361897269                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1408387                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196212                       # Number of bytes of host memory used
+host_seconds                                   155.80                       # Real time elapsed on the host
+host_tick_rate                              837126295                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219430973                       # Number of instructions simulated
 sim_seconds                                  0.130427                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 6cbe3be3b..57a70ac98 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 32ad08600..517f22714 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:37:25
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:04:39
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 96e63da4b..512b20d78 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 894535                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201656                       # Number of bytes of host memory used
-host_seconds                                   245.30                       # Real time elapsed on the host
-host_tick_rate                             1023073835                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 527252                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203888                       # Number of bytes of host memory used
+host_seconds                                   416.18                       # Real time elapsed on the host
+host_tick_rate                              603014388                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219430973                       # Number of instructions simulated
 sim_seconds                                  0.250962                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses             1928                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.332384                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1361.446792                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           77197730                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55870.331950                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses             4694                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.710588                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1455.283940                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          173494375                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses            4736                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.062047                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2033.146081                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.022985                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              6596                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52003.272804                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency