diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/70.twolf/ref | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/70.twolf/ref')
33 files changed, 675 insertions, 652 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 8ab14c5fa..84850f694 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index d80de6314..21f9ae246 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 19:04:15 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:01:01 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index b78683303..53d449590 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 137731 # Simulator instruction rate (inst/s) -host_mem_usage 254052 # Number of bytes of host memory used -host_seconds 667.27 # Real time elapsed on the host -host_tick_rate 60742348 # Simulator tick rate (ticks/s) +host_inst_rate 197293 # Simulator instruction rate (inst/s) +host_mem_usage 267004 # Number of bytes of host memory used +host_seconds 465.82 # Real time elapsed on the host +host_tick_rate 87010339 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated sim_ticks 40531279000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 59.146483 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 7590519 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 11539980 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 57928840 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 84258569 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.activity 91.670040 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 27308571 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 59.146483 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 4489525 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 7590519 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 138 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 2806970 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 7883251 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 11539980 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.execution_unit.executions 57928840 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 7433715 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 9804 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 4938 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066327 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 2191.171348 # Cy system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 458252 # Number of Multipy Operations Executed system.cpu.numCycles 81062559 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 84258569 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 68427361 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 27951091 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 53111468 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 33262621 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 47799938 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 32674404 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 48388155 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63236282 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 17826277 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 26883065 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 54179494 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 27951091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53111468 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33262621 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 47799938 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 32674404 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 48388155 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63236282 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 17826277 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 26883065 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 54179494 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 0fa57e7b8..9d0ac975a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index c1340f659..ec6c3f639 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:40 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c969dd1c3..8dc1a35af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141441 # Simulator instruction rate (inst/s) -host_mem_usage 212592 # Number of bytes of host memory used -host_seconds 595.16 # Real time elapsed on the host -host_tick_rate 57448767 # Simulator tick rate (ticks/s) +host_inst_rate 274016 # Simulator instruction rate (inst/s) +host_mem_usage 208580 # Number of bytes of host memory used +host_seconds 307.21 # Real time elapsed on the host +host_tick_rate 111296260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.034191 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1952481 # Nu system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3636559 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:count 91903055 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. -system.cpu.commit.COM:int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.COM:loads 19996198 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 26497301 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 2243 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 1459.544584 # Cy system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 25031 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle +system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 32239873 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 31883201 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 10134 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 17386201 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12448390 # Number of branches executed -system.cpu.iew.EXEC:nop 11194543 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.455255 # Inst execution rate -system.cpu.iew.EXEC:refs 32240280 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7278167 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 87558338 # num instructions consuming a value -system.cpu.iew.WB:count 97422402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.737743 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 64595544 # num instructions producing a value -system.cpu.iew.WB:rate 1.424676 # insts written-back per cycle -system.cpu.iew.WB:sent 98290476 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 12448390 # Number of branches executed +system.cpu.iew.exec_nop 11194543 # number of nop insts executed +system.cpu.iew.exec_rate 1.455255 # Inst execution rate +system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed +system.cpu.iew.exec_stores 7278167 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 2710213 # system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 64595544 # num instructions producing a value +system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle +system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 134796814 # number of integer regfile reads system.cpu.int_regfile_writes 73485618 # number of integer regfile writes system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1618550 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.490981 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 30709271 # Nu system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.rate 1.490981 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 5098 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency @@ -477,27 +477,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 68382153 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 9732280 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 457 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 186605606 # The number of ROB reads system.cpu.rob.rob_writes 260771760 # The number of ROB writes system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 06628f244..8a2d657fe 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 3667c8fef..17088cdf6 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1609489 # Simulator instruction rate (inst/s) -host_mem_usage 222008 # Number of bytes of host memory used -host_seconds 57.10 # Real time elapsed on the host -host_tick_rate 804741446 # Simulator tick rate (ticks/s) +host_inst_rate 5556970 # Simulator instruction rate (inst/s) +host_mem_usage 199664 # Number of bytes of host memory used +host_seconds 16.54 # Real time elapsed on the host +host_tick_rate 2778455792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cab9a523d..f2a594baf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 5503045c3..c82977f3d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:48 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:08 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 2aaa18b18..ea7e649f7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 559604 # Simulator instruction rate (inst/s) -host_mem_usage 229724 # Number of bytes of host memory used -host_seconds 164.23 # Real time elapsed on the host -host_tick_rate 723015392 # Simulator tick rate (ticks/s) +host_inst_rate 2623121 # Simulator instruction rate (inst/s) +host_mem_usage 207408 # Number of bytes of host memory used +host_seconds 35.04 # Real time elapsed on the host +host_tick_rate 3389091421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 4765 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 0db8749b7..6ac40b8d3 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 0ed791575..573beb25f 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:17:05 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:27:04 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index cc80406fa..cc9da8f96 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 145657 # Simulator instruction rate (inst/s) -host_mem_usage 262540 # Number of bytes of host memory used -host_seconds 1295.30 # Real time elapsed on the host -host_tick_rate 97115047 # Simulator tick rate (ticks/s) +host_inst_rate 180598 # Simulator instruction rate (inst/s) +host_mem_usage 218960 # Number of bytes of host memory used +host_seconds 1044.69 # Real time elapsed on the host +host_tick_rate 120412102 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188669132 # Number of instructions simulated sim_seconds 0.125793 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 9866046 # Nu system.cpu.BPredUnit.condPredicted 86389460 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 110931092 # Number of BP lookups system.cpu.BPredUnit.usedRAS 4559844 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 40284207 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1785335 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 224388172 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.840880 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 224388172 # Number of insts commited each cycle -system.cpu.commit.COM:count 188683520 # Number of instructions committed -system.cpu.commit.COM:fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1848934 # Number of function calls committed. -system.cpu.commit.COM:int_insts 150271150 # Number of committed integer instructions. -system.cpu.commit.COM:loads 29852009 # Number of loads committed -system.cpu.commit.COM:membars 22408 # Number of memory barriers committed -system.cpu.commit.COM:refs 42499167 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 9726959 # The number of times a branch was mispredicted +system.cpu.commit.branches 40284207 # Number of branches committed +system.cpu.commit.bw_lim_events 1785335 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 188683520 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1635919 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 179794570 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 224388172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.840880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 224388172 # Number of insts commited each cycle +system.cpu.commit.count 188683520 # Number of instructions committed +system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1848934 # Number of function calls committed. +system.cpu.commit.int_insts 150271150 # Number of committed integer instructions. +system.cpu.commit.loads 29852009 # Number of loads committed +system.cpu.commit.membars 22408 # Number of memory barriers committed +system.cpu.commit.refs 42499167 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 188669132 # Number of Instructions Simulated system.cpu.committedInsts_total 188669132 # Number of Instructions Simulated system.cpu.cpi 1.333479 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1827 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.338856 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1387.955871 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.338856 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 50846441 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31573.330399 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 1387.955871 # Cy system.cpu.dcache.total_refs 50888924 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 36464777 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 170249 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 17878904 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 446600367 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 82272510 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 104826667 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 27129630 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 707147 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 824217 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 36464777 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 170249 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 17878904 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 446600367 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 82272510 # Number of cycles decode is idle +system.cpu.decode.RunCycles 104826667 # Number of cycles decode is running +system.cpu.decode.SquashCycles 27129630 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 707147 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 824217 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 3509 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.620491 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1270.764699 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.620491 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 38679890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23669.425633 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 38675903 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 68606 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 53273558 # Number of branches executed -system.cpu.iew.EXEC:nop 53064 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.964190 # Inst execution rate -system.cpu.iew.EXEC:refs 53783248 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 13613267 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 284801843 # num instructions consuming a value -system.cpu.iew.WB:count 238885590 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.499623 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 142293577 # num instructions producing a value -system.cpu.iew.WB:rate 0.949517 # insts written-back per cycle -system.cpu.iew.WB:sent 240138833 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 11160275 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 53273558 # Number of branches executed +system.cpu.iew.exec_nop 53064 # number of nop insts executed +system.cpu.iew.exec_rate 0.964190 # Inst execution rate +system.cpu.iew.exec_refs 53783248 # number of memory reference insts executed +system.cpu.iew.exec_stores 13613267 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 19997 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 50338304 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 2241625 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 5462392 # system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 284801843 # num instructions consuming a value +system.cpu.iew.wb_count 238885590 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.499623 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 142293577 # num instructions producing a value +system.cpu.iew.wb_rate 0.949517 # insts written-back per cycle +system.cpu.iew.wb_sent 240138833 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 542109498 # number of integer regfile reads system.cpu.int_regfile_writes 231159216 # number of integer regfile writes system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 250420912 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1580075 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 251517801 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.995639 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 251517801 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.995367 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 250420912 # Type of FU issued system.cpu.iq.fp_alu_accesses 1881090 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 3742288 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 1821838 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 2251906 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1580075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 250119897 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 750424252 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 237063752 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 177594377 # Nu system.cpu.iq.iqSquashedInstsIssued 226843 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 629835 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 280770553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 251517801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.995639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 251517801 # Number of insts issued each cycle +system.cpu.iq.rate 0.995367 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses 3652 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.055915 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1832.230344 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3.029186 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.055915 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 5336 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34289.940022 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency @@ -495,27 +495,27 @@ system.cpu.misc_regfile_writes 825084 # nu system.cpu.numCycles 251586407 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 895052 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 180981200 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 614225 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 90974405 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 956098353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 414819410 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 416850208 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96863032 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 27129630 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5258013 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235869004 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 13790121 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 942308232 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2658319 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 23659926 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2454002 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 895052 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 180981200 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 614225 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 90974405 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 956098353 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 414819410 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 416850208 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 96863032 # Number of cycles rename is running +system.cpu.rename.SquashCycles 27129630 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5258013 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 235869004 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 13790121 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 942308232 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2658319 # count of serializing insts renamed +system.cpu.rename.skidInsts 23659926 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2454002 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 591075726 # The number of ROB reads system.cpu.rob.rob_writes 764090765 # The number of ROB writes system.cpu.timesIdled 1409 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini index d713880d3..283406dc2 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout index 8b4af0675..03f12e59d 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:22:24 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:30:09 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index bbc7121bd..bdd5452bf 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1042149 # Simulator instruction rate (inst/s) -host_mem_usage 250372 # Number of bytes of host memory used -host_seconds 181.04 # Real time elapsed on the host -host_tick_rate 569523249 # Simulator tick rate (ticks/s) +host_inst_rate 3821612 # Simulator instruction rate (inst/s) +host_mem_usage 209488 # Number of bytes of host memory used +host_seconds 49.37 # Real time elapsed on the host +host_tick_rate 2088466357 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188670900 # Number of instructions simulated sim_seconds 0.103107 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 177007633 # nu system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index 0ecbfede5..c22086808 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 9ae12354c..a62fdd8f9 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:25:36 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:31:09 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 1ea8a3c3d..6b9d8abcc 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 569972 # Simulator instruction rate (inst/s) -host_mem_usage 258100 # Number of bytes of host memory used -host_seconds 330.17 # Real time elapsed on the host -host_tick_rate 702907358 # Simulator tick rate (ticks/s) +host_inst_rate 2299830 # Simulator instruction rate (inst/s) +host_mem_usage 217236 # Number of bytes of host memory used +host_seconds 81.83 # Real time elapsed on the host +host_tick_rate 2836221203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188185929 # Number of instructions simulated sim_seconds 0.232077 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1789 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.332911 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332911 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 3051 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.560538 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 3453 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.051044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 177007633 # nu system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index f4dfd8899..9f7fb86bc 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:39 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:03 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 5f3549812..df028f09a 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1142521 # Simulator instruction rate (inst/s) -host_mem_usage 224208 # Number of bytes of host memory used -host_seconds 169.31 # Real time elapsed on the host -host_tick_rate 571263026 # Simulator tick rate (ticks/s) +host_inst_rate 4299467 # Simulator instruction rate (inst/s) +host_mem_usage 202100 # Number of bytes of host memory used +host_seconds 44.99 # Real time elapsed on the host +host_tick_rate 2149737482 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 163703467 # nu system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_mem_refs 76733959 # number of memory refs system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls +system.cpu.workload.num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index c8439f7fb..1787724e4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index a4abb12dd..748c08434 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:19 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:21:39 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index f02c69451..9ba399fb8 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 498703 # Simulator instruction rate (inst/s) -host_mem_usage 231920 # Number of bytes of host memory used -host_seconds 387.90 # Real time elapsed on the host -host_tick_rate 697549821 # Simulator tick rate (ticks/s) +host_inst_rate 2425845 # Simulator instruction rate (inst/s) +host_mem_usage 209848 # Number of bytes of host memory used +host_seconds 79.74 # Real time elapsed on the host +host_tick_rate 3393094719 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270577 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 1575 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.302050 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.777135 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency @@ -182,10 +182,10 @@ system.cpu.l2cache.demand_mshr_misses 5173 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.081736 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,6 +227,6 @@ system.cpu.num_int_register_writes 163703466 # nu system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_mem_refs 76733959 # number of memory refs system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls +system.cpu.workload.num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 61dc4a8fe..15faea73a 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index d11a4f41f..09f414a42 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:12:16 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:39:55 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 4edd15028..84b97ca66 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118324 # Simulator instruction rate (inst/s) -host_mem_usage 224536 # Number of bytes of host memory used -host_seconds 1870.83 # Real time elapsed on the host -host_tick_rate 57079180 # Simulator tick rate (ticks/s) +host_inst_rate 200454 # Simulator instruction rate (inst/s) +host_mem_usage 220376 # Number of bytes of host memory used +host_seconds 1104.31 # Real time elapsed on the host +host_tick_rate 96698720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.106785 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3071588 # Nu system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2318001 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 190318905 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.163116 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 190318905 # Number of insts commited each cycle -system.cpu.commit.COM:count 221363017 # Number of instructions committed -system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 220339606 # Number of committed integer instructions. -system.cpu.commit.COM:loads 56649590 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 77165306 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted +system.cpu.commit.branches 12326943 # Number of branches committed +system.cpu.commit.bw_lim_events 2318001 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 190318905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.163116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 190318905 # Number of insts commited each cycle +system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. +system.cpu.commit.loads 56649590 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 77165306 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 1955 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.341442 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.341442 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 1398.546932 # Cy system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 57112679 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 420105654 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 67048451 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 60385094 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 23161998 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 5772681 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 57112679 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 420105654 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 67048451 # Number of cycles decode is idle +system.cpu.decode.RunCycles 60385094 # Number of cycles decode is running +system.cpu.decode.SquashCycles 23161998 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 5772681 # Number of cycles decode is unblocking system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked @@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses 5384 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.784044 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.784044 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency @@ -212,21 +212,13 @@ system.cpu.icache.total_refs 27524838 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 15858881 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.303230 # Inst execution rate -system.cpu.iew.EXEC:refs 90240962 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 23196856 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 371845968 # num instructions consuming a value -system.cpu.iew.WB:count 275965139 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.599241 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 222825226 # num instructions producing a value -system.cpu.iew.WB:rate 1.292148 # insts written-back per cycle -system.cpu.iew.WB:sent 277010234 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 15858881 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 1.303230 # Inst execution rate +system.cpu.iew.exec_refs 90240962 # number of memory reference insts executed +system.cpu.iew.exec_stores 23196856 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions @@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 16601009 # system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 371845968 # num instructions consuming a value +system.cpu.iew.wb_count 275965139 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.599241 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 222825226 # num instructions producing a value +system.cpu.iew.wb_rate 1.292148 # insts written-back per cycle +system.cpu.iew.wb_sent 277010234 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 516469209 # number of integer regfile reads system.cpu.int_regfile_writes 283974364 # number of integer regfile writes system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 281846671 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 2813875 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 213480903 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.320243 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 213480903 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.319688 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 281846671 # Type of FU issued system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 2813875 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses @@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined 174039946 # Nu system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 213480903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.320243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 213480903 # Number of insts issued each cycle +system.cpu.iq.rate 1.319688 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency @@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses 5223 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.074157 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.074157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency @@ -447,27 +447,27 @@ system.cpu.misc_regfile_writes 844 # nu system.cpu.numCycles 213570763 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 18060003 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 21564374 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 74887260 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1054491347 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 409882715 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 430914543 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 57380379 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 23161998 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39968831 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 196551134 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 11087102 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1043404245 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 22432 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1444 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 83221554 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1312 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 18060003 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 21564374 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 74887260 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 1054491347 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 409882715 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 430914543 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 57380379 # Number of cycles rename is running +system.cpu.rename.SquashCycles 23161998 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 39968831 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 196551134 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 11087102 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1043404245 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 22432 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1444 # count of serializing insts renamed +system.cpu.rename.skidInsts 83221554 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1312 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 583734688 # The number of ROB reads system.cpu.rob.rob_writes 814640460 # The number of ROB writes system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 9f05df433..6d11a44d3 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:38:23 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 0c54c7d41..80e0c67c1 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1396551 # Simulator instruction rate (inst/s) -host_mem_usage 231332 # Number of bytes of host memory used -host_seconds 158.51 # Real time elapsed on the host -host_tick_rate 828940820 # Simulator tick rate (ticks/s) +host_inst_rate 3098099 # Simulator instruction rate (inst/s) +host_mem_usage 209904 # Number of bytes of host memory used +host_seconds 71.45 # Real time elapsed on the host +host_tick_rate 1838915708 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 232532006 # nu system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 2709fd0f4..040454ea4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 72c0f8f4d..ac8ab44c7 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:30:33 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index bbd74268b..b2588e568 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 920852 # Simulator instruction rate (inst/s) -host_mem_usage 239052 # Number of bytes of host memory used -host_seconds 240.39 # Real time elapsed on the host -host_tick_rate 1043974445 # Simulator tick rate (ticks/s) +host_inst_rate 1944621 # Simulator instruction rate (inst/s) +host_mem_usage 217656 # Number of bytes of host memory used +host_seconds 113.83 # Real time elapsed on the host +host_tick_rate 2204625935 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1905 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 4694 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 4735 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 232532006 # nu system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- |