diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/70.twolf/ref | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/70.twolf/ref')
21 files changed, 668 insertions, 661 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 86946de65..72f88064b 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -186,7 +186,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr index a263a334f..10a04a681 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr @@ -4,3 +4,6 @@ warn: Prefetching currently unimplemented For more information see: http://www.m5sim.org/warn/8028fa22 warn: Write Hints currently unimplemented For more information see: http://www.m5sim.org/warn/cfb3293b +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index b3cc1783c..78d80c7fd 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:41 -M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr -M5 started Jun 25 2010 15:39:42 -M5 executing on zooks -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:18:42 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -26,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124
\ No newline at end of file +122 123 124 Exiting @ tick 98337080000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index cb03716ca..4e98786e0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48476 # Simulator instruction rate (inst/s) -host_mem_usage 156444 # Number of bytes of host memory used -host_seconds 1895.84 # Real time elapsed on the host -host_tick_rate 51872539 # Simulator tick rate (ticks/s) +host_inst_rate 33745 # Simulator instruction rate (inst/s) +host_mem_usage 211108 # Number of bytes of host memory used +host_seconds 2723.45 # Real time elapsed on the host +host_tick_rate 36107563 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098342 # Number of seconds simulated -sim_ticks 98342168000 # Number of ticks simulated +sim_seconds 0.098337 # Number of seconds simulated +sim_ticks 98337080000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064 system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 185972249 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 117544888 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2843109 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 95.455386 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 95.460360 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43625545 # Number of Integer instructions committed @@ -42,28 +42,28 @@ system.cpu.comStores 6502695 # Nu system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.140128 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.140128 # CPI: Total CPI of All Threads +system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48523.157895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23048500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56219.741797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53219.741797 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104512500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98935500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55269.280206 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128998500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121984000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352015 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.851487 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55269.280206 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128998500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2334 # number of overall misses +system.cpu.dcache.overall_hits 26495062 # number of overall hits +system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2239 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121984000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.851487 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -126,10 +126,10 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27218.382183 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 235874500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits @@ -145,10 +145,10 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27218.382183 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 235874500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits @@ -158,14 +158,14 @@ system.cpu.icache.demand_mshr_misses 8577 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697630 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.745723 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27218.382183 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 101754085 # number of overall hits -system.cpu.icache.overall_miss_latency 235874500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses system.cpu.icache.overall_misses 8666 # number of overall misses system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6743 # number of replacements system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.745723 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8938543 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.467262 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.467262 # IPC: Total IPC of All Threads +system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,48 +201,48 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52212.528604 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91267500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52167.646099 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159789500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52265.765766 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5801500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.971947 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52183.953440 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 251057000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -252,16 +252,16 @@ system.cpu.l2cache.demand_mshr_misses 4811 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2025.851218 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.722274 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52183.953440 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5989 # number of overall hits -system.cpu.l2cache.overall_miss_latency 251057000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4811 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -271,34 +271,34 @@ system.cpu.l2cache.overall_mshr_misses 4811 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2039.573492 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 196684337 # number of cpu cycles simulated -system.cpu.runCycles 187745794 # Number of cycles cpu stages are processed. +system.cpu.numCycles 196674161 # number of cpu cycles simulated +system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94921538 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.739147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 104523823 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.857068 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 103191853 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.534280 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 170147206 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.492244 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 104781281 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.726169 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 196684337 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index c80e576a2..d1980c8dc 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -353,7 +353,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index adb770d42..9e4298349 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:04:41 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:11:51 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -30,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124
\ No newline at end of file +122 123 124 Exiting @ tick 40700936000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 317b399da..88a37a0c5 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 133236 # Simulator instruction rate (inst/s) -host_mem_usage 211268 # Number of bytes of host memory used -host_seconds 631.81 # Real time elapsed on the host -host_tick_rate 63779599 # Simulator tick rate (ticks/s) +host_inst_rate 126678 # Simulator instruction rate (inst/s) +host_mem_usage 211676 # Number of bytes of host memory used +host_seconds 664.52 # Real time elapsed on the host +host_tick_rate 61249065 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040297 # Number of seconds simulated -sim_ticks 40296654500 # Number of ticks simulated +sim_seconds 0.040701 # Number of seconds simulated +sim_ticks 40700936000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 11915731 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15874516 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1889856 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14601933 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19578482 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2865019 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 73200115 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.255504 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.951469 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 35335976 48.77% 48.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 18219580 25.15% 73.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 7350657 10.15% 84.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3843959 5.31% 89.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2026400 2.80% 92.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1285963 1.77% 93.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 738665 1.02% 94.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 745593 1.03% 95.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 35882998 49.02% 49.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 18421131 25.17% 74.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 7399939 10.11% 84.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3793003 5.18% 89.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2033143 2.78% 92.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1324637 1.81% 94.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 734587 1.00% 95.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 745658 1.02% 96.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2865019 3.91% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 73200115 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1876719 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 56257070 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads +system.cpu.cpi 0.967001 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.967001 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 23361768 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30148.648649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32165.686275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23360880 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26772000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 888 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16404500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 35665.614165 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35983.686319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493027 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 288035500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001242 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8076 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 62863500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1747 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13315.768510 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29862871 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35119.087461 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29853907 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 314807500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000300 # miss rate for demand accesses +system.cpu.dcache.demand_misses 8964 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6707 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 79268000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2257 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356506 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1460.250343 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29862871 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35119.087461 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29815560 # number of overall hits -system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9190 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29853907 # number of overall hits +system.cpu.dcache.overall_miss_latency 314807500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000300 # miss rate for overall accesses +system.cpu.dcache.overall_misses 8964 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6707 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 79268000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2257 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use -system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1460.250343 # Cycle average of tags in use +system.cpu.dcache.total_refs 29853953 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31794123 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 4195548 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13275 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3138319 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162326104 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39347421 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29437279 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8092915 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 219867 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31798312 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31394253 # DTB hits -system.cpu.dtb.data_misses 399870 # DTB misses +system.cpu.dtb.data_hits 31419824 # DTB hits +system.cpu.dtb.data_misses 378488 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24584547 # DTB read accesses +system.cpu.dtb.read_accesses 24587008 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24185700 # DTB read hits -system.cpu.dtb.read_misses 398847 # DTB read misses -system.cpu.dtb.write_accesses 7209576 # DTB write accesses +system.cpu.dtb.read_hits 24209579 # DTB read hits +system.cpu.dtb.read_misses 377429 # DTB read misses +system.cpu.dtb.write_accesses 7211304 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7208553 # DTB write hits -system.cpu.dtb.write_misses 1023 # DTB write misses -system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched -system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7210245 # DTB write hits +system.cpu.dtb.write_misses 1059 # DTB write misses +system.cpu.fetch.Branches 19578482 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19042269 # Number of cache lines fetched +system.cpu.fetch.Cycles 49581999 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 482446 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167417229 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2029251 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.240516 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19042269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13652580 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.056675 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 81293030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.087442 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 50753371 62.43% 62.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3139837 3.86% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1896166 2.33% 68.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3230989 3.97% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4381492 5.39% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1498123 1.84% 79.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1855484 2.28% 82.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1657938 2.04% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12879630 15.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 81293030 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19042269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15754.189443 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11879.245840 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19031110 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175801000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11159 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1002 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120657500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10157 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1873.694004 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency -system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses -system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19042269 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15754.189443 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency +system.cpu.icache.demand_hits 19031110 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175801000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses +system.cpu.icache.demand_misses 11159 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1002 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120657500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10157 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.756087 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1548.466977 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19042269 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15754.189443 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19038605 # number of overall hits -system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses -system.cpu.icache.overall_misses 11140 # number of overall misses -system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses +system.cpu.icache.overall_hits 19031110 # number of overall hits +system.cpu.icache.overall_miss_latency 175801000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses +system.cpu.icache.overall_misses 11159 # number of overall misses +system.cpu.icache.overall_mshr_hits 1002 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120657500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10157 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8223 # number of replacements -system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8241 # number of replacements +system.cpu.icache.sampled_refs 10157 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use -system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1548.466977 # Cycle average of tags in use +system.cpu.icache.total_refs 19031110 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12897175 # Number of branches executed -system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate -system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7211217 # Number of stores executed +system.cpu.idleCycles 108843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12932923 # Number of branches executed +system.cpu.iew.EXEC:nop 12752202 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.252024 # Inst execution rate +system.cpu.iew.EXEC:refs 31851727 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7212953 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value -system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back +system.cpu.iew.WB:consumers 91350917 # num instructions consuming a value +system.cpu.iew.WB:count 100121723 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.722506 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65858228 # num instructions producing a value -system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle -system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 66001625 # num instructions producing a value +system.cpu.iew.WB:rate 1.229968 # insts written-back per cycle +system.cpu.iew.WB:sent 100959925 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2058548 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 308035 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33906352 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1495689 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10659868 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148158966 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24638774 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2167496 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101917138 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 147063 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8092915 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 184741 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 837967 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2533 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 262394 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13871939 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4157173 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 262394 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 456488 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1602060 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.034125 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.034125 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580885 62.05% 62.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474250 0.46% 62.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786793 2.68% 65.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387015 2.29% 67.58% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25334190 24.34% 92.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346496 7.06% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 104084634 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1605159 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015422 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 233517 14.55% 14.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 750460 46.75% 95.23% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 76517 4.77% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 81293030 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280364 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539599 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 34420666 42.77% 42.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 18632497 23.15% 65.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 11734091 14.58% 80.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6720766 8.35% 88.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5079668 6.31% 95.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2378591 2.96% 98.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1227784 1.53% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 245969 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 34992329 43.04% 43.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 18915944 23.27% 66.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 11753054 14.46% 80.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6613669 8.14% 88.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5112903 6.29% 95.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2406334 2.96% 98.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1201307 1.48% 99.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 249469 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 48021 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate -system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 81293030 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.278652 # Inst issue rate +system.cpu.iq.iqInstsAdded 135406325 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104084634 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 439 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50573904 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 302099 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47258027 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19049819 # ITB accesses +system.cpu.itb.fetch_accesses 19042340 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19049745 # ITB hits -system.cpu.itb.fetch_misses 74 # ITB misses +system.cpu.itb.fetch_hits 19042269 # ITB hits +system.cpu.itb.fetch_misses 71 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,105 +343,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34688.510393 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31520.207852 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60080500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1732 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54593000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1732 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10667 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34283.465725 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.788761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116529500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318646 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3399 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105647000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318646 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3399 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 512500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 465000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.094427 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12399 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34420.190996 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7268 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 176610000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413824 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5131 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 160240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5131 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000413 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2302.538330 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.547355 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12399 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34420.190996 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7254 # number of overall hits -system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5123 # number of overall misses +system.cpu.l2cache.overall_hits 7268 # number of overall hits +system.cpu.l2cache.overall_miss_latency 176610000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413824 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5131 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 160240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5131 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3463 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2316.085685 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7253 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 80593310 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17615087 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5052814 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33906352 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10659868 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 81401873 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1958439 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed -system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1204670 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40603212 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 943778 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202469078 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157094553 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115390079 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28386104 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8092915 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2247194 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 46962718 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5166 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 474 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4950472 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 408aa067d..3a1e6de05 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 927d0a698..258e66688 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:41:35 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:58:58 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -26,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124
\ No newline at end of file +122 123 124 Exiting @ tick 118742021000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index ab73f2477..b08531811 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 611509 # Simulator instruction rate (inst/s) -host_mem_usage 195576 # Number of bytes of host memory used -host_seconds 150.29 # Real time elapsed on the host -host_tick_rate 790125098 # Simulator tick rate (ticks/s) +host_inst_rate 1269659 # Simulator instruction rate (inst/s) +host_mem_usage 210612 # Number of bytes of host memory used +host_seconds 72.38 # Real time elapsed on the host +host_tick_rate 1640438984 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118747 # Number of seconds simulated -sim_ticks 118747246000 # Number of ticks simulated +sim_seconds 0.118742 # Number of seconds simulated +sim_ticks 118742021000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 475 # nu system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 98784000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 93492000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 55005.806163 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123158000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 116441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352056 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1442.022508 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352059 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1442.035674 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55005.806163 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2334 # number of overall misses +system.cpu.dcache.overall_hits 26495062 # number of overall hits +system.cpu.dcache.overall_miss_latency 123158000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2239 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 116441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.035674 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692396 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1418.025998 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.692403 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1418.041181 # Average occupied blocks per context system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.041181 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -180,20 +180,20 @@ system.cpu.l2cache.ReadReq_misses 3043 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 832000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 640000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.909179 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -213,10 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 4791 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061290 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2008.334369 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.724981 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2056.260143 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.724287 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -232,14 +232,14 @@ system.cpu.l2cache.overall_mshr_misses 4791 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3105 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2069.984431 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237494492 # number of cpu cycles simulated +system.cpu.numCycles 237484042 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index 4b18512b5..43ac38afd 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 93238e8c4..a3b84a071 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:39:29 +M5 compiled Aug 26 2010 13:52:30 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:54:23 M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +30,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232029492000 because target called exit() +122 123 124 Exiting @ tick 232028062000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index f93740715..156b8dc2a 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1662173 # Simulator instruction rate (inst/s) -host_mem_usage 213456 # Number of bytes of host memory used -host_seconds 112.10 # Real time elapsed on the host -host_tick_rate 2069793412 # Simulator tick rate (ticks/s) +host_inst_rate 1713926 # Simulator instruction rate (inst/s) +host_mem_usage 214560 # Number of bytes of host memory used +host_seconds 108.72 # Real time elapsed on the host +host_tick_rate 2134224518 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186333855 # Number of instructions simulated -sim_seconds 0.232029 # Number of seconds simulated -sim_ticks 232029492000 # Number of ticks simulated +sim_seconds 0.232028 # Number of seconds simulated +sim_ticks 232028062000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 690 # nu system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 12385567 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 63112000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1127 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 59731000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000091 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1127 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 12385593 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54659.328564 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency -system.cpu.dcache.demand_hits 42025057 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 99316000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54639.865997 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency +system.cpu.dcache.demand_hits 42025083 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97860000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1817 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1791 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 93865000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 92487000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1817 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1791 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.333153 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1364.595461 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.333155 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1364.601520 # Average occupied blocks per context system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54659.328564 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54639.865997 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 42025057 # number of overall hits -system.cpu.dcache.overall_miss_latency 99316000 # number of overall miss cycles +system.cpu.dcache.overall_hits 42025083 # number of overall hits +system.cpu.dcache.overall_miss_latency 97860000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1817 # number of overall misses +system.cpu.dcache.overall_misses 1791 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 93865000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 92487000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1817 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1791 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1364.595461 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1364.601520 # Cycle average of tags in use system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 3051 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.560534 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1147.972858 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.560536 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1147.977742 # Average occupied blocks per context system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1506 # number of replacements system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1147.972858 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.977742 # Cycle average of tags in use system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -166,20 +166,20 @@ system.cpu.l2cache.ReadReq_misses 2361 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 27 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1404000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 52000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 27 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1080000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 40000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.588813 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582348 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -199,10 +199,10 @@ system.cpu.l2cache.demand_mshr_misses 3461 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050372 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1650.604772 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2.043757 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 1672.604273 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2.043764 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 3461 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2342 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2368 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1652.648529 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1674.648036 # Cycle average of tags in use system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 464058984 # number of cpu cycles simulated +system.cpu.numCycles 464056124 # number of cpu cycles simulated system.cpu.num_insts 186333855 # Number of instructions executed system.cpu.num_refs 42511846 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 1d3f0204a..dc0731aa6 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 04fab7689..a4fbf8115 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:37:15 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:51 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270578335000 because target called exit() +122 123 124 Exiting @ tick 270576960000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 791de009c..46f688248 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 890462 # Simulator instruction rate (inst/s) -host_mem_usage 197912 # Number of bytes of host memory used -host_seconds 217.24 # Real time elapsed on the host -host_tick_rate 1245520491 # Simulator tick rate (ticks/s) +host_inst_rate 953366 # Simulator instruction rate (inst/s) +host_mem_usage 216056 # Number of bytes of host memory used +host_seconds 202.91 # Real time elapsed on the host +host_tick_rate 1333500122 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270578 # Number of seconds simulated -sim_ticks 270578335000 # Number of ticks simulated +sim_seconds 0.270577 # Number of seconds simulated +sim_ticks 270576960000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,23 +21,23 @@ system.cpu.dcache.ReadReq_mshr_misses 498 # nu system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. @@ -49,37 +49,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.302049 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1237.193190 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76709909 # number of overall hits -system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles +system.cpu.dcache.overall_hits 76709933 # number of overall hits +system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1599 # number of overall misses +system.cpu.dcache.overall_misses 1575 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.777132 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1591.566647 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.777135 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency @@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -158,20 +158,11 @@ system.cpu.l2cache.ReadReq_misses 4095 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -191,10 +182,10 @@ system.cpu.l2cache.demand_mshr_misses 5173 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.081095 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2657.327524 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.000455 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -210,14 +201,14 @@ system.cpu.l2cache.overall_mshr_misses 5173 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541156670 # number of cpu cycles simulated +system.cpu.numCycles 541153920 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 06c7e5e67..c1e1fc55b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 3e7c2cb07..705b33507 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:26:25 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +31,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250962187000 because target called exit() +122 123 124 Exiting @ tick 250960757000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index fb0c1905f..24bf72eb4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1720597 # Simulator instruction rate (inst/s) -host_mem_usage 232456 # Number of bytes of host memory used -host_seconds 127.53 # Real time elapsed on the host -host_tick_rate 1967834922 # Simulator tick rate (ticks/s) +host_inst_rate 935562 # Simulator instruction rate (inst/s) +host_mem_usage 217504 # Number of bytes of host memory used +host_seconds 234.54 # Real time elapsed on the host +host_tick_rate 1069990696 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 219431024 # Number of instructions simulated -sim_seconds 0.250962 # Number of seconds simulated -sim_ticks 250962187000 # Number of ticks simulated +sim_seconds 0.250961 # Number of seconds simulated +sim_ticks 250960757000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 327 # nu system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20514126 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89824000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1604 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 85012000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1604 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 88368000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 83634000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55848.783014 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency -system.cpu.dcache.demand_hits 77195807 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 107844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 55846.719160 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency +system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 106388000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1931 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 102050500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 100672500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1931 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.332873 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1363.445907 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1363.451646 # Average occupied blocks per context system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55848.783014 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55846.719160 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 77195807 # number of overall hits -system.cpu.dcache.overall_miss_latency 107844000 # number of overall miss cycles +system.cpu.dcache.overall_hits 77195833 # number of overall hits +system.cpu.dcache.overall_miss_latency 106388000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1931 # number of overall misses +system.cpu.dcache.overall_misses 1905 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 102050500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 100672500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1931 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1363.445907 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.451646 # Cycle average of tags in use system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 7 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 4694 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.710587 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1455.283090 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1455.289171 # Average occupied blocks per context system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2836 # number of replacements system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.283090 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.289171 # Cycle average of tags in use system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,20 +148,11 @@ system.cpu.l2cache.ReadReq_misses 3160 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.593053 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -181,10 +172,10 @@ system.cpu.l2cache.demand_mshr_misses 4738 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062108 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2035.144824 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021758 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2058.146657 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.021757 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -200,14 +191,14 @@ system.cpu.l2cache.overall_mshr_misses 4738 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3138 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2035.166582 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.168414 # Cycle average of tags in use system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501924374 # number of cpu cycles simulated +system.cpu.numCycles 501921514 # number of cpu cycles simulated system.cpu.num_insts 219431024 # Number of instructions executed system.cpu.num_refs 77165306 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |