diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/70.twolf/ref | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/70.twolf/ref')
12 files changed, 455 insertions, 349 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 752831326..10ff9c3eb 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index f4a8bde29..0262f8e2d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13022932 # Number of BTB hits -global.BPredUnit.BTBLookups 16938031 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1944645 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14588431 # Number of conditional branches predicted -global.BPredUnit.lookups 19441115 # Number of BP lookups -global.BPredUnit.usedRAS 1715741 # Number of times the RAS was used to get a target. -host_inst_rate 140839 # Simulator instruction rate (inst/s) -host_mem_usage 205524 # Number of bytes of host memory used -host_seconds 597.70 # Real time elapsed on the host -host_tick_rate 68085854 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17320747 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5158870 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33916617 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10592327 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 13010658 # Number of BTB hits +global.BPredUnit.BTBLookups 16925459 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1191 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1944478 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted +global.BPredUnit.lookups 19422613 # Number of BP lookups +global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target. +host_inst_rate 134486 # Simulator instruction rate (inst/s) +host_mem_usage 187512 # Number of bytes of host memory used +host_seconds 625.94 # Real time elapsed on the host +host_tick_rate 64866574 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10556967 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040695 # Number of seconds simulated -sim_ticks 40694900000 # Number of ticks simulated +sim_seconds 0.040602 # Number of seconds simulated +sim_ticks 40602361500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2814383 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2830089 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73372540 +system.cpu.commit.COM:committed_per_cycle.samples 73220545 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36054158 4913.85% - 1 18224800 2483.87% - 2 7501822 1022.43% - 3 3901009 531.67% - 4 2128189 290.05% - 5 1274528 173.71% - 6 744433 101.46% - 7 729218 99.39% - 8 2814383 383.57% + 0 35958705 4911.01% + 1 18165534 2480.93% + 2 7495163 1023.64% + 3 3905368 533.37% + 4 2115499 288.92% + 5 1290804 176.29% + 6 741318 101.24% + 7 718065 98.07% + 8 2830089 386.52% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1932230 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1932029 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55717434 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.966851 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.966851 # CPI: Total CPI of All Threads +system.cpu.cpi 0.964650 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.964650 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23356209 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5569 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23355709 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4533000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 500 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2784500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6495002 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 24564.959569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5850.134771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493147 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 45568000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6101 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 10852000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8854.743083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23304645 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4480500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 115 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6494991 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 24985.167206 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5885.922330 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493137 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 46322500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 10912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13325.436607 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13302.637946 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29851211 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21274.309979 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29848856 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 50101000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 29800142 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 21526.694915 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29797782 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 50803000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2355 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6224 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 2360 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6227 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13695500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2355 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2360 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29851211 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21274.309979 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29800142 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 21526.694915 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29848856 # number of overall hits -system.cpu.dcache.overall_miss_latency 50101000 # number of overall miss cycles +system.cpu.dcache.overall_hits 29797782 # number of overall hits +system.cpu.dcache.overall_miss_latency 50803000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2355 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6224 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 2360 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6227 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13695500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2355 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2360 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 160 # number of replacements +system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.130010 # Cycle average of tags in use -system.cpu.dcache.total_refs 29848978 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.011880 # Cycle average of tags in use +system.cpu.dcache.total_refs 29797909 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3820626 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12575 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3037417 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162462210 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39463165 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29936850 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8016661 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 44953 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 151900 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 19441115 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19217268 # Number of cache lines fetched -system.cpu.fetch.Cycles 50163624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 510483 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167309935 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2078673 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238866 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19217268 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14738673 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.055677 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 105 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3766232 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12611 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3034294 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162205348 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39405972 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29900475 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 7983383 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45169 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 147867 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31800987 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 31340580 # DTB hits +system.cpu.dtb.misses 460407 # DTB misses +system.cpu.dtb.read_accesses 24617799 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 24158583 # DTB read hits +system.cpu.dtb.read_misses 459216 # DTB read misses +system.cpu.dtb.write_accesses 7183188 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 7181997 # DTB write hits +system.cpu.dtb.write_misses 1191 # DTB write misses +system.cpu.fetch.Branches 19422613 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19195045 # Number of cache lines fetched +system.cpu.fetch.Cycles 50102609 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239183 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.057366 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81389202 +system.cpu.fetch.rateDist.samples 81203929 system.cpu.fetch.rateDist.min_value 0 - 0 50442849 6197.73% - 1 3127409 384.25% - 2 2013333 247.37% - 3 3501649 430.24% - 4 4585592 563.42% - 5 1499931 184.29% - 6 2042041 250.90% - 7 1854540 227.86% - 8 12321858 1513.94% + 0 50296438 6193.84% + 1 3127485 385.14% + 2 2009190 247.43% + 3 3499443 430.95% + 4 4580392 564.06% + 5 1498651 184.55% + 6 2040206 251.24% + 7 1851037 227.95% + 8 12301087 1514.84% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19216915 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5291.898608 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3156.958250 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19206855 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 53236500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 19194697 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5285.401314 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3152.011551 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19184655 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 53076000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10060 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 353 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 31759000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10042 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 348 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31652500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10060 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 10042 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1909.230119 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1910.441645 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19216915 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5291.898608 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency -system.cpu.icache.demand_hits 19206855 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 53236500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 19194697 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5285.401314 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency +system.cpu.icache.demand_hits 19184655 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 53076000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses -system.cpu.icache.demand_misses 10060 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 353 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 31759000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10042 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 348 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31652500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10060 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10042 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19216915 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5291.898608 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency +system.cpu.icache.overall_accesses 19194697 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5285.401314 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19206855 # number of overall hits -system.cpu.icache.overall_miss_latency 53236500 # number of overall miss cycles +system.cpu.icache.overall_hits 19184655 # number of overall hits +system.cpu.icache.overall_miss_latency 53076000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses -system.cpu.icache.overall_misses 10060 # number of overall misses -system.cpu.icache.overall_mshr_hits 353 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 31759000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10042 # number of overall misses +system.cpu.icache.overall_mshr_hits 348 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31652500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10060 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10042 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -217,183 +229,187 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8146 # number of replacements -system.cpu.icache.sampled_refs 10060 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8129 # number of replacements +system.cpu.icache.sampled_refs 10042 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1551.624399 # Cycle average of tags in use -system.cpu.icache.total_refs 19206855 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1547.586704 # Cycle average of tags in use +system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 435727 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12761226 # Number of branches executed -system.cpu.iew.EXEC:nop 12552336 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.247935 # Inst execution rate -system.cpu.iew.EXEC:refs 31899012 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7188094 # Number of stores executed +system.cpu.idleCycles 554685 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12760718 # Number of branches executed +system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.249722 # Inst execution rate +system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7184817 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90808493 # num instructions consuming a value -system.cpu.iew.WB:count 99646578 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.722903 # average fanout of values written-back +system.cpu.iew.WB:consumers 90693698 # num instructions consuming a value +system.cpu.iew.WB:count 99568419 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723301 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65645732 # num instructions producing a value -system.cpu.iew.WB:rate 1.224322 # insts written-back per cycle -system.cpu.iew.WB:sent 100573545 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2105709 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 285403 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33916617 # Number of dispatched load instructions +system.cpu.iew.WB:producers 65598879 # num instructions producing a value +system.cpu.iew.WB:rate 1.226153 # insts written-back per cycle +system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33831723 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1714541 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10592327 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147619094 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24710918 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2203361 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101568426 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 132795 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 1731846 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10556967 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147344437 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24666810 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2188087 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101482299 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 133099 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8016661 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 165683 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 7983383 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 165893 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 838013 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1487 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 843499 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1537 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 249026 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13882204 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4089632 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 249026 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 202527 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1903182 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.034286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.034286 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 103771787 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 250644 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9811 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13797310 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4054272 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.036646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.036646 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued - IntAlu 64228940 61.89% # Type of FU issued - IntMult 473017 0.46% # Type of FU issued + IntAlu 64195239 61.92% # Type of FU issued + IntMult 473046 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2790055 2.69% # Type of FU issued - FloatCmp 115633 0.11% # Type of FU issued - FloatCvt 2376207 2.29% # Type of FU issued - FloatMult 305676 0.29% # Type of FU issued - FloatDiv 755062 0.73% # Type of FU issued - FloatSqrt 323 0.00% # Type of FU issued - MemRead 25409003 24.49% # Type of FU issued - MemWrite 7317864 7.05% # Type of FU issued + FloatAdd 2788829 2.69% # Type of FU issued + FloatCmp 115617 0.11% # Type of FU issued + FloatCvt 2372095 2.29% # Type of FU issued + FloatMult 305683 0.29% # Type of FU issued + FloatDiv 755148 0.73% # Type of FU issued + FloatSqrt 322 0.00% # Type of FU issued + MemRead 25353594 24.46% # Type of FU issued + MemWrite 7310806 7.05% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1978136 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.019062 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1973729 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.019039 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 311313 15.74% # attempts to use FU when none available + IntAlu 311847 15.80% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 546 0.03% # attempts to use FU when none available + FloatAdd 478 0.02% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 3483 0.18% # attempts to use FU when none available - FloatMult 2460 0.12% # attempts to use FU when none available - FloatDiv 833660 42.14% # attempts to use FU when none available + FloatCvt 2917 0.15% # attempts to use FU when none available + FloatMult 2390 0.12% # attempts to use FU when none available + FloatDiv 832522 42.18% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 753551 38.09% # attempts to use FU when none available - MemWrite 73123 3.70% # attempts to use FU when none available + MemRead 750992 38.05% # attempts to use FU when none available + MemWrite 72583 3.68% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81389202 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81203929 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35308856 4338.27% - 1 18677963 2294.89% - 2 11652538 1431.71% - 3 6999702 860.03% - 4 4887440 600.50% - 5 2229546 273.94% - 6 1377818 169.29% - 7 217468 26.72% - 8 37871 4.65% + 0 35188418 4333.34% + 1 18662979 2298.29% + 2 11625415 1431.63% + 3 6937118 854.28% + 4 4927347 606.79% + 5 2234432 275.16% + 6 1373348 169.12% + 7 215389 26.52% + 8 39483 4.86% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.275007 # Inst issue rate -system.cpu.iq.iqInstsAdded 135066329 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103771787 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.276667 # Inst issue rate +system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50270340 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 231965 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 50027749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 225448 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47066497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 1741 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4485.353245 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2485.353245 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7809000 # number of ReadExReq miss cycles +system.cpu.iq.iqSquashedOperandsExamined 46827412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19195118 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 19195045 # ITB hits +system.cpu.itb.misses 73 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4523.342939 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2523.342939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7848000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1741 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4327000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4378000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1741 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10559 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4274.193548 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2274.193548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14575000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.322947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10547 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4263.929619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.929619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14540000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.323315 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7755000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.323315 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 118 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 531000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4430.894309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2430.894309 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 545000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 118 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 295000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 299000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 118 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 106 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 105 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 106 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 105 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.172948 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.172603 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12300 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4345.563968 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7149 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.418780 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5151 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12282 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4351.409135 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7137 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.418906 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5145 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.418780 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5151 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12098000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.418906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5145 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12300 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4345.563968 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12282 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4351.409135 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7149 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.418780 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5151 # number of overall misses +system.cpu.l2cache.overall_hits 7137 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.418906 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5145 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.418780 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5151 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12098000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.418906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5145 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -406,30 +422,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3290 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3285 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2252.890734 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7149 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2248.754865 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81389202 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1683934 # Number of cycles rename is blocking +system.cpu.numCycles 81203929 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1032549 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40751116 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 970163 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202965992 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157380306 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115963922 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28805465 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8016661 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2127274 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47536561 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4752 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4689522 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed -system.cpu.timesIdled 283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40689840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 938076 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202669964 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157140698 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115798524 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28770212 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 7983383 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2084846 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47371163 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4726 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 465 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4645791 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 454 # count of temporary serializing insts renamed +system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 3cb797e6a..8fbd6f60b 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=twolf smred @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index acfa7c9dd..127e45547 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 935813 # Simulator instruction rate (inst/s) -host_mem_usage 150648 # Number of bytes of host memory used -host_seconds 98.21 # Real time elapsed on the host -host_tick_rate 467904361 # Simulator tick rate (ticks/s) +host_inst_rate 2451408 # Simulator instruction rate (inst/s) +host_mem_usage 179100 # Number of bytes of host memory used +host_seconds 37.49 # Real time elapsed on the host +host_tick_rate 1225693454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903057 # Number of instructions simulated +sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951528000 # Number of ticks simulated +sim_ticks 45951567500 # Number of ticks simulated +system.cpu.dtb.accesses 26497334 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 26497301 # DTB hits +system.cpu.dtb.misses 33 # DTB misses +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 91903136 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 91903089 # ITB hits +system.cpu.itb.misses 47 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 91903057 # number of cpu cycles simulated -system.cpu.num_insts 91903057 # Number of instructions executed -system.cpu.num_refs 26537109 # Number of memory references +system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 56cac7865..da35f8268 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 1f35acc4a..beacdcee0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1713530 # Simulator instruction rate (inst/s) -host_mem_usage 204416 # Number of bytes of host memory used -host_seconds 53.63 # Real time elapsed on the host -host_tick_rate 2211088665 # Simulator tick rate (ticks/s) +host_inst_rate 1574277 # Simulator instruction rate (inst/s) +host_mem_usage 186464 # Number of bytes of host memory used +host_seconds 58.38 # Real time elapsed on the host +host_tick_rate 2031398471 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903057 # Number of instructions simulated +sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118590 # Number of seconds simulated -sim_ticks 118589598000 # Number of ticks simulated +sim_ticks 118589630000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.457790 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.457531 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks -system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 26497334 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 26497301 # DTB hits +system.cpu.dtb.misses 33 # DTB misses +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # ms system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency -system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits +system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 91894548 # number of overall hits +system.cpu.icache.overall_hits 91894580 # number of overall hits system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.474486 # Cycle average of tags in use -system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1418.474247 # Cycle average of tags in use +system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 91903137 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 91903090 # ITB hits +system.cpu.itb.misses 47 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2014.752255 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2014.751911 # Cycle average of tags in use system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 118589598000 # number of cpu cycles simulated -system.cpu.num_insts 91903057 # Number of instructions executed -system.cpu.num_refs 26537109 # Number of memory references +system.cpu.numCycles 118589630000 # number of cpu cycles simulated +system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 3dcf027c2..aad9a4c07 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=twolf smred @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index c41d3b35f..655a20772 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 673586 # Simulator instruction rate (inst/s) -host_mem_usage 150548 # Number of bytes of host memory used -host_seconds 287.17 # Real time elapsed on the host -host_tick_rate 336792536 # Simulator tick rate (ticks/s) +host_inst_rate 1618953 # Simulator instruction rate (inst/s) +host_mem_usage 181044 # Number of bytes of host memory used +host_seconds 119.48 # Real time elapsed on the host +host_tick_rate 809478979 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435973 # Number of instructions simulated +sim_insts 193435005 # Number of instructions simulated sim_seconds 0.096718 # Number of seconds simulated -sim_ticks 96717986000 # Number of ticks simulated +sim_ticks 96718067000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 193435973 # number of cpu cycles simulated -system.cpu.num_insts 193435973 # Number of instructions executed -system.cpu.num_refs 76732959 # Number of memory references +system.cpu.numCycles 193436135 # number of cpu cycles simulated +system.cpu.num_insts 193435005 # Number of instructions executed +system.cpu.num_refs 76733003 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index f878587c3..6b3948164 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 16:48:51 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 23:36:54 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 96717986000 because target called exit() +Exiting @ tick 96718067000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 1e251ac7c..8769743d0 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 7c9f3f182..bb82b8cc2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1154889 # Simulator instruction rate (inst/s) -host_mem_usage 206344 # Number of bytes of host memory used -host_seconds 167.49 # Real time elapsed on the host -host_tick_rate 1614378740 # Simulator tick rate (ticks/s) +host_inst_rate 1002711 # Simulator instruction rate (inst/s) +host_mem_usage 188412 # Number of bytes of host memory used +host_seconds 192.91 # Real time elapsed on the host +host_tick_rate 1401662479 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435973 # Number of instructions simulated +sim_insts 193435005 # Number of instructions simulated sim_seconds 0.270398 # Number of seconds simulated -sim_ticks 270397855000 # Number of ticks simulated +sim_ticks 270397899000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.402461 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.402352 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks -system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses @@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # ms system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15766.526736 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency -system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits +system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses @@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 12268 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193423706 # number of overall hits +system.cpu.icache.overall_hits 193423750 # number of overall hits system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses @@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.726914 # Cycle average of tags in use -system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.726789 # Cycle average of tags in use +system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2649.703709 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2649.703495 # Cycle average of tags in use system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270397855000 # number of cpu cycles simulated -system.cpu.num_insts 193435973 # Number of instructions executed -system.cpu.num_refs 76732959 # Number of memory references +system.cpu.numCycles 270397899000 # number of cpu cycles simulated +system.cpu.num_insts 193435005 # Number of instructions executed +system.cpu.num_refs 76733003 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index c89e9c783..656615235 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 16:55:52 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 23:38:54 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 270397855000 because target called exit() +Exiting @ tick 270397899000 because target called exit() |