diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/long/70.twolf/ref | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/long/70.twolf/ref')
6 files changed, 1117 insertions, 1115 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ba1de8238..cae861e0e 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 18:07:05 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 19:50:53 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 32092296500 because target called exit() +122 123 124 Exiting @ tick 33574995000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 5aa0ca1ff..9b4ccbc94 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.032092 # Number of seconds simulated -sim_ticks 32092296500 # Number of ticks simulated +sim_seconds 0.033575 # Number of seconds simulated +sim_ticks 33574995000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73581 # Simulator instruction rate (inst/s) -host_tick_rate 28051508 # Simulator tick rate (ticks/s) -host_mem_usage 250560 # Number of bytes of host memory used -host_seconds 1144.05 # Real time elapsed on the host +host_inst_rate 75399 # Simulator instruction rate (inst/s) +host_tick_rate 30072740 # Simulator tick rate (ticks/s) +host_mem_usage 250632 # Number of bytes of host memory used +host_seconds 1116.46 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25665074 # DTB read hits -system.cpu.dtb.read_misses 532377 # DTB read misses +system.cpu.dtb.read_hits 25910068 # DTB read hits +system.cpu.dtb.read_misses 487884 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26197451 # DTB read accesses -system.cpu.dtb.write_hits 7413229 # DTB write hits -system.cpu.dtb.write_misses 1159 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 7414388 # DTB write accesses -system.cpu.dtb.data_hits 33078303 # DTB hits -system.cpu.dtb.data_misses 533536 # DTB misses -system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 33611839 # DTB accesses -system.cpu.itb.fetch_hits 19743768 # ITB hits -system.cpu.itb.fetch_misses 86 # ITB misses +system.cpu.dtb.read_accesses 26397952 # DTB read accesses +system.cpu.dtb.write_hits 7442430 # DTB write hits +system.cpu.dtb.write_misses 947 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7443377 # DTB write accesses +system.cpu.dtb.data_hits 33352498 # DTB hits +system.cpu.dtb.data_misses 488831 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 33841329 # DTB accesses +system.cpu.itb.fetch_hits 20391081 # ITB hits +system.cpu.itb.fetch_misses 82 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 19743854 # ITB accesses +system.cpu.itb.fetch_accesses 20391163 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 64184594 # number of cpu cycles simulated +system.cpu.numCycles 67149991 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 19638238 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14616795 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1934317 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 16315844 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12540710 # Number of BTB hits +system.cpu.BPredUnit.lookups 20043424 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 14890335 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1886616 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 16546187 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12995160 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1821712 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2747 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 21008427 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 166538758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19638238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14362422 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 30824536 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 9451370 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4886757 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 19743768 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 631936 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 64091521 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.598452 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.236190 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1876944 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2472 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 21676746 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 172437485 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20043424 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14872104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 31892042 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10307497 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5295116 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 20391081 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 650323 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 67056836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.571512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.236226 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33266985 51.91% 51.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3147764 4.91% 56.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2102748 3.28% 60.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3556460 5.55% 65.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4397921 6.86% 72.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1522590 2.38% 74.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1866548 2.91% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1731844 2.70% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12498661 19.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 35164794 52.44% 52.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3176485 4.74% 57.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2538345 3.79% 60.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3535941 5.27% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4282691 6.39% 72.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1574198 2.35% 74.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1997484 2.98% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1705355 2.54% 80.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 13081543 19.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 64091521 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305965 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.594684 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23134324 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3873003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 28813163 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 914553 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7356478 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3062607 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 67056836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298487 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.567945 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23902898 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4218142 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 29787412 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 970752 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8177632 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3156419 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 160619110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43067 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 7356478 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24847542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1029661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 27972484 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2879319 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 153930695 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 698435 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1852837 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 113010867 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 199187244 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 187702425 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11484819 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 166261756 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43031 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8177632 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25731687 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1160543 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6023 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 28902105 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3078846 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 159343297 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 846266 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1904805 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 117303281 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 206166674 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 193984489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12182185 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 44583506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 529 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 520 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7678386 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 31845410 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9896316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6196134 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1567027 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 129169470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 502 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107327436 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 534587 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44082208 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35410789 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 113 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 64091521 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.674596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.788065 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 48875920 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 516 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8753950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33541628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10395963 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7223070 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2102878 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 134779237 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 499 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107642256 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 461690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 49489496 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42823427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 67056836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.605239 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.754849 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23013905 35.91% 35.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13200417 20.60% 56.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9655349 15.06% 71.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7236543 11.29% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5456935 8.51% 91.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2848092 4.44% 95.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1848148 2.88% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 707452 1.10% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124680 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24956395 37.22% 37.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14036514 20.93% 58.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10136000 15.12% 73.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7177120 10.70% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5400162 8.05% 92.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2788229 4.16% 96.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1798139 2.68% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 642461 0.96% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121816 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 64091521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 67056836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206408 12.63% 12.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6500 0.40% 13.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5851 0.36% 13.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 847321 51.84% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 65.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 476077 29.13% 94.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91992 5.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 201993 12.31% 12.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 250 0.02% 12.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6175 0.38% 12.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5518 0.34% 13.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 850319 51.81% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 486670 29.65% 94.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90238 5.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 65553727 61.08% 61.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 486899 0.45% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2819079 2.63% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2427572 2.26% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 312395 0.29% 66.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763362 0.71% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27299077 25.44% 92.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7549954 7.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 65718321 61.05% 61.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491419 0.46% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2837753 2.64% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114927 0.11% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2460943 2.29% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 308030 0.29% 66.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 776022 0.72% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27323056 25.38% 92.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7611460 7.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107327436 # Type of FU issued -system.cpu.iq.rate 1.672168 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1634345 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015228 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265519684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 162160015 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 94997457 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15395641 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 11288937 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7141397 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 100830916 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8130858 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1254132 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107642256 # Type of FU issued +system.cpu.iq.rate 1.603012 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1641163 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015246 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 268833280 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 171996090 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 95630473 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15610921 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12638151 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7243335 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 101046338 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8237074 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1306070 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11849212 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9154 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 349266 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3395213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13545430 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9202 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 431066 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3894860 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10688 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10948 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7356478 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94659 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31189 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 141503695 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 872227 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 31845410 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9896316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 502 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12366 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 349266 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1814664 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342809 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2157473 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104568587 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26198042 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2758849 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8177632 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205335 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 131722 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 147421220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 680146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 33541628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10395963 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 498 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 98656 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 431066 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1771181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 338775 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2109956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 105130467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26398523 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2511789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12333723 # number of nop insts executed -system.cpu.iew.exec_refs 33612538 # number of memory reference insts executed -system.cpu.iew.exec_branches 13292388 # Number of branches executed -system.cpu.iew.exec_stores 7414496 # Number of stores executed -system.cpu.iew.exec_rate 1.629185 # Inst execution rate -system.cpu.iew.wb_sent 103278074 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102138854 # cumulative count of insts written-back -system.cpu.iew.wb_producers 68941212 # num instructions producing a value -system.cpu.iew.wb_consumers 95281048 # num instructions consuming a value +system.cpu.iew.exec_nop 12641484 # number of nop insts executed +system.cpu.iew.exec_refs 33841971 # number of memory reference insts executed +system.cpu.iew.exec_branches 13292827 # Number of branches executed +system.cpu.iew.exec_stores 7443448 # Number of stores executed +system.cpu.iew.exec_rate 1.565607 # Inst execution rate +system.cpu.iew.wb_sent 103975635 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102873808 # cumulative count of insts written-back +system.cpu.iew.wb_producers 69418102 # num instructions producing a value +system.cpu.iew.wb_consumers 96250402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.591330 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.723556 # average fanout of values written-back +system.cpu.iew.wb_rate 1.532000 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721224 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 49602328 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55519927 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1920862 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 56735043 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.619864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.379821 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1873181 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 58879204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.560875 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.342568 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 26448220 46.62% 46.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12595125 22.20% 68.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5584191 9.84% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2979320 5.25% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1760489 3.10% 87.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1489209 2.62% 89.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 769969 1.36% 91.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 774387 1.36% 92.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4334133 7.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 27960283 47.49% 47.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13480171 22.89% 70.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5538232 9.41% 79.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2736120 4.65% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1795830 3.05% 87.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1555437 2.64% 90.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 775440 1.32% 91.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 776613 1.32% 92.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4261078 7.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 56735043 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 58879204 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4334133 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4261078 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 193905253 # The number of ROB reads -system.cpu.rob.rob_writes 290432006 # The number of ROB writes -system.cpu.timesIdled 2283 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93073 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 202040068 # The number of ROB reads +system.cpu.rob.rob_writes 303073761 # The number of ROB writes +system.cpu.timesIdled 2271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93155 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.762471 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762471 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311525 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311525 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 141097992 # number of integer regfile reads -system.cpu.int_regfile_writes 77269821 # number of integer regfile writes -system.cpu.fp_regfile_reads 6208793 # number of floating regfile reads -system.cpu.fp_regfile_writes 6125599 # number of floating regfile writes -system.cpu.misc_regfile_reads 715479 # number of misc regfile reads +system.cpu.cpi 0.797698 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.797698 # CPI: Total CPI of All Threads +system.cpu.ipc 1.253607 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.253607 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 141776374 # number of integer regfile reads +system.cpu.int_regfile_writes 77917804 # number of integer regfile writes +system.cpu.fp_regfile_reads 6238511 # number of floating regfile reads +system.cpu.fp_regfile_writes 6227605 # number of floating regfile writes +system.cpu.misc_regfile_reads 722508 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8662 # number of replacements -system.cpu.icache.tagsinuse 1591.987817 # Cycle average of tags in use -system.cpu.icache.total_refs 19731988 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1863.266100 # Average number of references to valid blocks. +system.cpu.icache.replacements 8679 # number of replacements +system.cpu.icache.tagsinuse 1593.583704 # Cycle average of tags in use +system.cpu.icache.total_refs 20379337 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10611 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1920.585901 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1591.987817 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777338 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 19731988 # number of ReadReq hits -system.cpu.icache.demand_hits 19731988 # number of demand (read+write) hits -system.cpu.icache.overall_hits 19731988 # number of overall hits -system.cpu.icache.ReadReq_misses 11780 # number of ReadReq misses -system.cpu.icache.demand_misses 11780 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 187835000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 187835000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 187835000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 19743768 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 19743768 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 19743768 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000597 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000597 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000597 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15945.246180 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15945.246180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15945.246180 # average overall miss latency +system.cpu.icache.occ_blocks::0 1593.583704 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.778117 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 20379337 # number of ReadReq hits +system.cpu.icache.demand_hits 20379337 # number of demand (read+write) hits +system.cpu.icache.overall_hits 20379337 # number of overall hits +system.cpu.icache.ReadReq_misses 11744 # number of ReadReq misses +system.cpu.icache.demand_misses 11744 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 187534500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 187534500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 187534500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 20391081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 20391081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 20391081 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000576 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000576 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000576 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15968.537125 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15968.537125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15968.537125 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1190 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1190 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1133 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1133 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1133 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10611 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10611 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10611 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124617500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124617500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124617500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124781500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000536 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000536 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000536 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11767.469311 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000520 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000520 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000520 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11759.636227 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1458.064990 # Cycle average of tags in use -system.cpu.dcache.total_refs 30892362 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13785.078983 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.306327 # Cycle average of tags in use +system.cpu.dcache.total_refs 31085202 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13864.942908 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1458.064990 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.355973 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24399260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493052 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30892312 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30892312 # number of overall hits -system.cpu.dcache.ReadReq_misses 942 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8051 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1459.306327 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356276 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24592075 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493081 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 46 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 31085156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 31085156 # number of overall hits +system.cpu.dcache.ReadReq_misses 927 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8022 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8993 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8993 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28111000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289250500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8949 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8949 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28002000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 288506000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 317361500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 317361500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24400202 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 316508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 316508000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 24593002 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30901305 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30901305 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.019608 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 29841.825902 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35927.276115 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 47 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 31094105 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 31094105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.001234 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.021277 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000288 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000288 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30207.119741 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35964.348043 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35289.836540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35289.836540 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35367.974075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35367.974075 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -411,72 +411,72 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6318 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6753 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6753 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 507 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 418 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6708 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6708 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2241 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16260000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61635000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61526000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77895000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77895000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77836000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77836000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.019608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.021277 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32071.005917 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35565.493364 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32043.222004 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35523.094688 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2392.328540 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7626 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3548 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.149380 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2396.251917 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7647 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.152872 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2374.739172 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.589369 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072471 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2378.668231 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.583686 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072591 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7618 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 7636 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7644 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7644 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3480 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5187 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5187 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119535500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59266000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178801500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178801500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11098 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 7661 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7661 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3484 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1708 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5192 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5192 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119676500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59253000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 178929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 178929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11120 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12831 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12831 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.313570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.984997 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.404255 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.404255 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.281609 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34719.390744 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34471.081550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34471.081550 # average overall miss latency +system.cpu.l2cache.demand_accesses 12853 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12853 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985574 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.403952 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.403952 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34350.315729 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34691.451991 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34462.538521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34462.538521 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3480 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5187 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5187 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3484 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1708 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5192 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5192 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108240500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53874500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162115000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162115000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108359500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162219500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162219500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984997 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.404255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.404255 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.591954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31560.925600 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.403952 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.403952 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.037887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31533.957845 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index b0302ff58..e55be2152 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:43 -gem5 started Jul 9 2011 04:18:32 +gem5 compiled Jul 15 2011 18:02:03 +gem5 started Jul 16 2011 04:01:57 gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 110281184000 because target called exit() +122 123 124 Exiting @ tick 109591303500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 0fe4beed8..9acd1c20e 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.110281 # Number of seconds simulated -sim_ticks 110281184000 # Number of ticks simulated +sim_seconds 0.109591 # Number of seconds simulated +sim_ticks 109591303500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65382 # Simulator instruction rate (inst/s) -host_tick_rate 38217412 # Simulator tick rate (ticks/s) -host_mem_usage 261804 # Number of bytes of host memory used -host_seconds 2885.63 # Real time elapsed on the host -sim_insts 188667677 # Number of instructions simulated +host_inst_rate 60659 # Simulator instruction rate (inst/s) +host_tick_rate 35235152 # Simulator tick rate (ticks/s) +host_mem_usage 261736 # Number of bytes of host memory used +host_seconds 3110.28 # Real time elapsed on the host +sim_insts 188667697 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 220562369 # number of cpu cycles simulated +system.cpu.numCycles 219182608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 104258409 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 82362571 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9936095 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86105898 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80445450 # Number of BTB hits +system.cpu.BPredUnit.lookups 103745786 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 81976338 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9943224 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 85671159 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80219991 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4758962 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 112969 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 46358647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 433367935 # Number of instructions fetch has processed -system.cpu.fetch.Branches 104258409 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 85204412 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 111822484 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35665794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36992864 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4756853 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 113204 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 46114245 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429912188 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103745786 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84976844 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 111330567 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35270728 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36699969 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 813 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 42110119 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2232853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 220504638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.132131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.672325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 41935754 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2246100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 219124425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.665143 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108888253 49.38% 49.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4953673 2.25% 51.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33070296 15.00% 66.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18447401 8.37% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9377183 4.25% 79.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12785261 5.80% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8550568 3.88% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4486115 2.03% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19945888 9.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108000297 49.29% 49.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5031394 2.30% 51.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33002073 15.06% 66.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18529573 8.46% 75.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9301462 4.24% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12648515 5.77% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8577033 3.91% 89.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4456570 2.03% 91.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19577508 8.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 220504638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.472694 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.964832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 55339748 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35376598 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 103212898 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1403307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 25172087 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14322485 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170339 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 440125451 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 696276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 25172087 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 64672455 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 776963 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29575154 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 95204893 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5103086 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 403993606 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 69868 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2710880 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 687477122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1728388844 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1709997227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18391617 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298062016 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 389415097 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2865354 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2816189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 26097925 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 51690689 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18730866 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8573671 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5359744 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 346939727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2374386 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267717167 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 907172 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 158256505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 384971202 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 738758 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 220504638 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.214111 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.476414 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 219124425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.473330 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.961434 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 55048245 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35099276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102750817 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1404892 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24821195 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14312217 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170214 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 436500086 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 694588 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 24821195 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 64323611 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 816730 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29228849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 94788839 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5145201 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 401098755 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 70910 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2783871 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 682579390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1716423376 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1698124875 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18298501 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298062048 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 384517342 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2790601 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2741243 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 25505966 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 51358732 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18498661 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9149940 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5397480 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344257456 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2323720 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266454796 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 912087 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 155278627 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 378105702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 688088 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 219124425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.215998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.473523 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 103384796 46.89% 46.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 39397520 17.87% 64.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35187917 15.96% 80.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 23179085 10.51% 91.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11803879 5.35% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4771097 2.16% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2229685 1.01% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 447825 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 102834 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102187705 46.63% 46.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 39549888 18.05% 64.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35231696 16.08% 80.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23077585 10.53% 91.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11566082 5.28% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4775373 2.18% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2189017 1.00% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 443166 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 103913 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 220504638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 219124425 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 341650 17.75% 17.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6050 0.31% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 35 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 4 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 93 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1226198 63.72% 81.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 350464 18.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 343002 18.52% 18.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6054 0.33% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 31 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 2 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 95 0.01% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1162999 62.81% 81.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 339535 18.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 208615296 77.92% 77.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925342 0.35% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 6202 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33026 0.01% 78.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166299 0.06% 78.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 260522 0.10% 78.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76108 0.03% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 471200 0.18% 78.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207528 0.08% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71629 0.03% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 327 0.00% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 42633393 15.92% 94.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14250295 5.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 207547424 77.89% 77.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 926133 0.35% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 6207 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.01% 78.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166254 0.06% 78.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 259347 0.10% 78.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76101 0.03% 78.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 470014 0.18% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207509 0.08% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71627 0.03% 78.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 78.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 42377903 15.90% 94.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14312934 5.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267717167 # Type of FU issued -system.cpu.iq.rate 1.213793 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1924494 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007189 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 754979573 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 505620151 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 248098864 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3791065 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2339721 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1843061 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267732701 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1908960 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1050657 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266454796 # Type of FU issued +system.cpu.iq.rate 1.215675 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1851718 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006949 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 751012737 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 499908383 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 246985878 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3785085 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2315100 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1843098 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266401517 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1904997 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1061099 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21838970 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7625 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 472350 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6083999 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21507010 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7624 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 380760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5851790 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 22 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 25172087 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44760 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3320 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 349368262 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3978827 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 51690689 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 18730866 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2350473 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 564 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2427 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 472350 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10008076 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1698961 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11707037 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 254915521 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 40541135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12801646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24821195 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25209 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3025 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 346635263 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3972949 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 51358732 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 18498661 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2299792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 380760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10016813 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1701165 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11717978 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 253656328 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 40286910 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12798468 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 54149 # number of nop insts executed -system.cpu.iew.exec_refs 54377446 # number of memory reference insts executed -system.cpu.iew.exec_branches 53214768 # Number of branches executed -system.cpu.iew.exec_stores 13836311 # Number of stores executed -system.cpu.iew.exec_rate 1.155753 # Inst execution rate -system.cpu.iew.wb_sent 251638468 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 249941925 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151812393 # num instructions producing a value -system.cpu.iew.wb_consumers 254020317 # num instructions consuming a value +system.cpu.iew.exec_nop 54087 # number of nop insts executed +system.cpu.iew.exec_refs 54182001 # number of memory reference insts executed +system.cpu.iew.exec_branches 53130827 # Number of branches executed +system.cpu.iew.exec_stores 13895091 # Number of stores executed +system.cpu.iew.exec_rate 1.157283 # Inst execution rate +system.cpu.iew.wb_sent 250510965 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 248828976 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151533747 # num instructions producing a value +system.cpu.iew.wb_consumers 253038401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.133203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.597639 # average fanout of values written-back +system.cpu.iew.wb_rate 1.135259 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598857 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188682065 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 160676887 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635628 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9797761 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 195332552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.965953 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.628775 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188682085 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 157943841 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635632 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9804994 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 194303231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.971070 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.635692 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109939001 56.28% 56.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 42858902 21.94% 78.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20127469 10.30% 88.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8563678 4.38% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5111696 2.62% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2060801 1.06% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1694385 0.87% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 852868 0.44% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4123752 2.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109217628 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 42594648 21.92% 78.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19958113 10.27% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8663175 4.46% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5049927 2.60% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2103639 1.08% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1719455 0.88% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 826115 0.43% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4170531 2.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 195332552 # Number of insts commited each cycle -system.cpu.commit.count 188682065 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 194303231 # Number of insts commited each cycle +system.cpu.commit.count 188682085 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498585 # Number of memory references committed -system.cpu.commit.loads 29851718 # Number of loads committed +system.cpu.commit.refs 42498593 # Number of memory references committed +system.cpu.commit.loads 29851722 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283916 # Number of branches committed +system.cpu.commit.branches 40283920 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115157 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115173 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4123752 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4170531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 540562551 # The number of ROB reads -system.cpu.rob.rob_writes 723954086 # The number of ROB writes -system.cpu.timesIdled 1712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 57731 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667677 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667677 # Number of Instructions Simulated -system.cpu.cpi 1.169052 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.169052 # CPI: Total CPI of All Threads -system.cpu.ipc 0.855394 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.855394 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1139481673 # number of integer regfile reads -system.cpu.int_regfile_writes 415646596 # number of integer regfile writes -system.cpu.fp_regfile_reads 2922802 # number of floating regfile reads -system.cpu.fp_regfile_writes 2492399 # number of floating regfile writes -system.cpu.misc_regfile_reads 524104390 # number of misc regfile reads -system.cpu.misc_regfile_writes 824502 # number of misc regfile writes -system.cpu.icache.replacements 1939 # number of replacements -system.cpu.icache.tagsinuse 1330.149475 # Cycle average of tags in use -system.cpu.icache.total_refs 42105837 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3648 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11542.170230 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 536753425 # The number of ROB reads +system.cpu.rob.rob_writes 718144719 # The number of ROB writes +system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58183 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667697 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667697 # Number of Instructions Simulated +system.cpu.cpi 1.161739 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.161739 # CPI: Total CPI of All Threads +system.cpu.ipc 0.860779 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.860779 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1134129060 # number of integer regfile reads +system.cpu.int_regfile_writes 413088145 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922495 # number of floating regfile reads +system.cpu.fp_regfile_writes 2493955 # number of floating regfile writes +system.cpu.misc_regfile_reads 519944359 # number of misc regfile reads +system.cpu.misc_regfile_writes 824510 # number of misc regfile writes +system.cpu.icache.replacements 1926 # number of replacements +system.cpu.icache.tagsinuse 1331.949680 # Cycle average of tags in use +system.cpu.icache.total_refs 41931510 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3631 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11548.198843 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1330.149475 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.649487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 42105837 # number of ReadReq hits -system.cpu.icache.demand_hits 42105837 # number of demand (read+write) hits -system.cpu.icache.overall_hits 42105837 # number of overall hits -system.cpu.icache.ReadReq_misses 4282 # number of ReadReq misses -system.cpu.icache.demand_misses 4282 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 102623500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 102623500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 102623500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 42110119 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 42110119 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 42110119 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23966.254087 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23966.254087 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23966.254087 # average overall miss latency +system.cpu.icache.occ_blocks::0 1331.949680 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.650366 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41931510 # number of ReadReq hits +system.cpu.icache.demand_hits 41931510 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41931510 # number of overall hits +system.cpu.icache.ReadReq_misses 4244 # number of ReadReq misses +system.cpu.icache.demand_misses 4244 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101763500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101763500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101763500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41935754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41935754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41935754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23978.204524 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23978.204524 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23978.204524 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 634 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 634 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 634 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3648 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3648 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3648 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 613 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 613 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 613 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3631 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3631 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3631 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74999500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74999500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74999500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74668500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74668500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74668500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20564.169650 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1408.348450 # Cycle average of tags in use -system.cpu.dcache.total_refs 51108076 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1850 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27625.987027 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1407.375528 # Cycle average of tags in use +system.cpu.dcache.total_refs 50844385 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1848 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27513.195346 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.348450 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343835 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 38699028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27661 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24640 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 51055775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 51055775 # number of overall hits -system.cpu.dcache.ReadReq_misses 1814 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1407.375528 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343598 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 38435222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356746 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27773 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24644 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 50791968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 50791968 # number of overall hits +system.cpu.dcache.ReadReq_misses 1795 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7541 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9354 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9354 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236790000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9336 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9336 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59271500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236699500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 296331500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 296331500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 38700842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 295971000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 295971000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 38437017 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27663 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24640 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 51065129 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 51065129 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 27775 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24644 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 50801304 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 50801304 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000183 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000183 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.000184 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000184 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33020.334262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31388.343721 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31679.655762 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31679.655762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31702.120823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31702.120823 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,69 +423,69 @@ system.cpu.dcache.avg_blocked_cycles::no_targets 20000 system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6451 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1035 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7504 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7504 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1089 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1850 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1850 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7488 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7488 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 760 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1088 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1848 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1848 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24275500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38318500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62594000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62524000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62524000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31946.710526 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35151.194853 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1929.340531 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2692 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.635587 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1932.871986 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1702 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2683 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.634365 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1926.279074 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.061457 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058785 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1929.817883 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.054103 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058893 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 1702 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1719 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1719 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2698 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3779 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3779 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92484500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37157500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129642000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129642000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1711 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1711 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2689 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1079 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3768 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3768 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92183000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37080500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129263500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129263500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4391 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1089 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5498 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.611930 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.992654 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.687341 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.687341 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.901032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.901032 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses 1088 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5479 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5479 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.612389 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.991728 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.687717 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.687717 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.517293 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.616311 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34305.599788 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34305.599788 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2683 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3764 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3764 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1079 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3754 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33564500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116951500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116951500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83139500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33503500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116643000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116643000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608528 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992654 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.684613 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.684613 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.609201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991728 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.685162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.685162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.186916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 13ca71321..fbdea3a95 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:15 -gem5 started Jul 9 2011 00:22:05 +gem5 compiled Jul 15 2011 18:01:24 +gem5 started Jul 15 2011 23:50:22 gem5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105045070000 because target called exit() +122 123 124 Exiting @ tick 105044494000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 05846252d..b774063aa 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105045 # Number of seconds simulated -sim_ticks 105045070000 # Number of ticks simulated +sim_seconds 0.105044 # Number of seconds simulated +sim_ticks 105044494000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49247 # Simulator instruction rate (inst/s) -host_tick_rate 23369426 # Simulator tick rate (ticks/s) -host_mem_usage 262348 # Number of bytes of host memory used -host_seconds 4494.98 # Real time elapsed on the host +host_inst_rate 56697 # Simulator instruction rate (inst/s) +host_tick_rate 26904511 # Simulator tick rate (ticks/s) +host_mem_usage 262296 # Number of bytes of host memory used +host_seconds 3904.35 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 210090141 # number of cpu cycles simulated +system.cpu.numCycles 210088989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits +system.cpu.BPredUnit.lookups 25906091 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25906091 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2877681 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23697798 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20934390 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30843739 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 261974302 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25906091 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20934390 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70794160 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26721651 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 84571192 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 411 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28839529 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 526028 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 210002245 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.077492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.256338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 141083594 67.18% 67.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4096564 1.95% 69.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3267465 1.56% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4473347 2.13% 72.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4273378 2.03% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4452036 2.12% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5454314 2.60% 79.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3065570 1.46% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39835977 18.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 210002245 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123310 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.246968 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45814663 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73297000 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 55964774 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11133134 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23792674 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 424975722 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23792674 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54914820 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 20522213 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23840 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57109649 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53639049 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 413573068 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30245146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20822120 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 438852783 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1070324075 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1058519342 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11804733 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 204489374 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1468 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1462 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108174037 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105166977 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38036544 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 93207180 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32406467 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 401191410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1447 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 281389101 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88945 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 179610706 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 379681728 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 210002245 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.339934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.371545 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69597365 33.14% 33.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 64957213 30.93% 64.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36846366 17.55% 81.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20444772 9.74% 91.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11872646 5.65% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4318388 2.06% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525465 0.73% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 350714 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 89316 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 210002245 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107872 3.66% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2450287 83.09% 86.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 390701 13.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1204241 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187252248 66.55% 66.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1588066 0.56% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67629899 24.03% 91.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23714647 8.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued -system.cpu.iq.rate 1.342042 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 281389101 # Type of FU issued +system.cpu.iq.rate 1.339381 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2948860 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770610110 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 574654249 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 273620025 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5208142 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6216706 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2514026 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 280509716 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2624004 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 16305906 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48517387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5787 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 69063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17520828 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45289 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23792674 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 691646 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 425399 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 401192857 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 138630 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105166977 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38036544 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1447 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 309021 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40843 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 69063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2486335 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 578919 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3065254 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 278324671 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66381551 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3064430 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed -system.cpu.iew.exec_branches 15748098 # Number of branches executed -system.cpu.iew.exec_stores 23391917 # Number of stores executed -system.cpu.iew.exec_rate 1.327442 # Inst execution rate -system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222890509 # num instructions producing a value -system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value +system.cpu.iew.exec_refs 89772300 # number of memory reference insts executed +system.cpu.iew.exec_branches 15687599 # Number of branches executed +system.cpu.iew.exec_stores 23390749 # Number of stores executed +system.cpu.iew.exec_rate 1.324794 # Inst execution rate +system.cpu.iew.wb_sent 277184129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 276134051 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222355020 # num instructions producing a value +system.cpu.iew.wb_consumers 373725319 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back +system.cpu.iew.wb_rate 1.314367 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.594969 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 179841994 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2877741 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 186209571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.188784 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.542023 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71071645 38.17% 38.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70044936 37.62% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18344188 9.85% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12667816 6.80% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5471591 2.94% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2983054 1.60% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2040122 1.10% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1105861 0.59% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2480358 1.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 186209571 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2480358 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 585604683 # The number of ROB reads -system.cpu.rob.rob_writes 827851683 # The number of ROB writes -system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 584934224 # The number of ROB reads +system.cpu.rob.rob_writes 826225881 # The number of ROB writes +system.cpu.timesIdled 1865 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 86744 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads -system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516476198 # number of integer regfile reads -system.cpu.int_regfile_writes 284804952 # number of integer regfile writes -system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads -system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes -system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads +system.cpu.cpi 0.949070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.949070 # CPI: Total CPI of All Threads +system.cpu.ipc 1.053663 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.053663 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515807985 # number of integer regfile reads +system.cpu.int_regfile_writes 284258767 # number of integer regfile writes +system.cpu.fp_regfile_reads 3504419 # number of floating regfile reads +system.cpu.fp_regfile_writes 2170248 # number of floating regfile writes +system.cpu.misc_regfile_reads 144660799 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4263 # number of replacements -system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use -system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks. +system.cpu.icache.replacements 4219 # number of replacements +system.cpu.icache.tagsinuse 1625.397975 # Cycle average of tags in use +system.cpu.icache.total_refs 28832382 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6182 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4663.924620 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits -system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28884352 # number of overall hits -system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses -system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7220 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency +system.cpu.icache.occ_blocks::0 1625.397975 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.793651 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28832382 # number of ReadReq hits +system.cpu.icache.demand_hits 28832382 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28832382 # number of overall hits +system.cpu.icache.ReadReq_misses 7147 # number of ReadReq misses +system.cpu.icache.demand_misses 7147 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7147 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 169208500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 169208500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 169208500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28839529 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28839529 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28839529 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000248 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000248 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000248 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23675.458234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23675.458234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23675.458234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 961 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 961 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 961 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6186 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6186 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125111000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000214 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000214 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000214 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20224.862593 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 50 # number of replacements -system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use -system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks. +system.cpu.dcache.replacements 49 # number of replacements +system.cpu.dcache.tagsinuse 1408.251063 # Cycle average of tags in use +system.cpu.dcache.total_refs 70379715 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1964 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35834.885438 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits -system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 70508699 # number of overall hits -system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses -system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7819 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1408.251063 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343811 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 49871091 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20508613 # number of WriteReq hits +system.cpu.dcache.demand_hits 70379704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 70379704 # number of overall hits +system.cpu.dcache.ReadReq_misses 713 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7117 # number of WriteReq misses +system.cpu.dcache.demand_misses 7830 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 7830 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 23577500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 188115500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 211693000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 211693000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 49871804 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 70387534 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 70387534 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33068.022440 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26431.853309 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27036.143040 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27036.143040 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 5551 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5862 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5862 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1968 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1968 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13701000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 55004000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 68705000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 68705000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34082.089552 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35123.882503 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2496.142499 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2832 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.754194 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2495.127708 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014791 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076145 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 2832 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2876 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2838 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2838 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3751 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5308 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128522000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53234000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 181756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 181756000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6583 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8146 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8146 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.569801 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.996161 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.651608 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.651608 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34263.396428 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34190.109184 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34241.899020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34241.899020 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3751 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116406500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48370500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 164777000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 164777000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569801 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.651608 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.651608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31033.457745 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31066.473988 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |