tests: update statistics for change caused by vsyscall support in x86

Caused by a slight change in memory layout.

3 files changed, 93 insertions, 96 deletions

diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index f70defe2b..6cbe3be3b 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -45,7 +45,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +79,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +113,6 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -152,7 +149,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index cfb8745b2..32ad08600 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:42:16
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+M5 compiled Nov  8 2009 16:16:58
+M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
+M5 started Nov  8 2009 16:37:25
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -27,4 +27,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 250961789000 because target called exit()
+122 123 124 Exiting @ tick 250962019000 because target called exit()
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index d0361bdaa..96e63da4b 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,84 +1,84 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 489241                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 228040                       # Number of bytes of host memory used
-host_seconds                                   448.51                       # Real time elapsed on the host
-host_tick_rate                              559541126                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 894535                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201656                       # Number of bytes of host memory used
+host_seconds                                   245.30                       # Real time elapsed on the host
+host_tick_rate                             1023073835                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219430973                       # Number of instructions simulated
 sim_seconds                                  0.250962                       # Number of seconds simulated
-sim_ticks                                250961789000                       # Number of ticks simulated
+sim_ticks                                250962019000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           56682001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               56681682                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       17823500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 55228.395062                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52226.851852                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               56681677                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       17894000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  319                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     16866500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                  324                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     16921500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             319                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses             324                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          20515729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              20514128                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      89656000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_hits              20514125                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      89824000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000078                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1601                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     84853000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses                1604                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     85012000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000078                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1601                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1604                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               40758.097149                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               40586.660358                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            77197730                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55978.906250                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                77195810                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       107479500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 55870.331950                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52870.072614                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                77195802                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       107718000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  1920                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  1928                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    101719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    101933500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1920                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             1928                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           77197730                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55978.906250                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55870.331950                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               77195810                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      107479500                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               77195802                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      107718000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 1920                       # number of overall misses
+system.cpu.dcache.overall_misses                 1928                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    101719500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    101933500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1920                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            1928                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                     27                       # number of replacements
-system.cpu.dcache.sampled_refs                   1894                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                     40                       # number of replacements
+system.cpu.dcache.sampled_refs                   1902                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1362.582472                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 77195836                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1361.446792                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 77195828                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                        2                       # number of writebacks
+system.cpu.dcache.writebacks                        7                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          173494375                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 39420.962931                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.252237                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 39420.856412                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              173489681                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      185042000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      185041500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000027                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 4694                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    170928500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    170928000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000027                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            4694                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -90,29 +90,29 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           173494375                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 39420.962931                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36414.252237                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 39420.856412                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               173489681                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       185042000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       185041500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000027                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  4694                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    170928500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    170928000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000027                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             4694                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          173494375                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 39420.962931                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36414.252237                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              173489681                       # number of overall hits
-system.cpu.icache.overall_miss_latency      185042000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      185041500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000027                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 4694                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    170928500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    170928000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000027                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            4694                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -120,29 +120,29 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   2836                       # number of replacements
 system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1455.283776                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1455.283940                       # Cycle average of tags in use
 system.cpu.icache.total_refs                173489681                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses            1575                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     81900000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     82056000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1575                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     63000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses              1578                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     63120000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1575                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              5013                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52005.066498                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses         1578                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses              5018                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52004.908170                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  1855                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     164232000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.629962                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_hits                  1860                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency     164231500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.629334                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                3158                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency    126320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.629962                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.629334                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3158                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             26                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
@@ -153,53 +153,53 @@ system.cpu.l2cache.UpgradeReq_misses               26                       # nu
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1040000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses           26                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses               2                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                   2                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses               7                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                   7                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.591895                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.593112                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               6588                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52003.380520                       # average overall miss latency
+system.cpu.l2cache.demand_accesses               6596                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52003.272804                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1855                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      246132000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.718427                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4733                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                   1860                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      246287500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.718011                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4736                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    189320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.718427                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4733                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    189440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.718011                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4736                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses              6588                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52003.380520                       # average overall miss latency
+system.cpu.l2cache.overall_accesses              6596                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52003.272804                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1855                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     246132000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.718427                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4733                       # number of overall misses
+system.cpu.l2cache.overall_hits                  1860                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     246287500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.718011                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4736                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    189320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.718427                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4733                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    189440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.718011                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4736                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3134                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3136                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2033.146295                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1855                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2033.169065                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1860                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        501923578                       # number of cpu cycles simulated
+system.cpu.numCycles                        501924038                       # number of cpu cycles simulated
 system.cpu.num_insts                        219430973                       # Number of instructions executed
 system.cpu.num_refs                          77165298                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls