diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/long/70.twolf/ref | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/long/70.twolf/ref')
9 files changed, 1122 insertions, 1115 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 01f3bf111..0fa57e7b8 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index b9f2d3d21..c1340f659 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:48 -M5 executing on burrito +M5 compiled Mar 17 2011 21:44:37 +M5 started Mar 17 2011 21:44:40 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -28,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 40631511500 because target called exit() +122 123 124 Exiting @ tick 34191076000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2fcd0832c..c969dd1c3 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 68515 # Simulator instruction rate (inst/s) -host_mem_usage 230924 # Number of bytes of host memory used -host_seconds 1228.63 # Real time elapsed on the host -host_tick_rate 33070698 # Simulator tick rate (ticks/s) +host_inst_rate 141441 # Simulator instruction rate (inst/s) +host_mem_usage 212592 # Number of bytes of host memory used +host_seconds 595.16 # Real time elapsed on the host +host_tick_rate 57448767 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040632 # Number of seconds simulated -sim_ticks 40631511500 # Number of ticks simulated +sim_seconds 0.034191 # Number of seconds simulated +sim_ticks 34191076000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 11932962 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15864027 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1214 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1885603 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14586720 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19564106 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1732867 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2884434 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3636559 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73022923 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.258551 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.953672 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 62672395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.466404 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 35697739 48.89% 48.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 18400471 25.20% 74.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 7461073 10.22% 84.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3811930 5.22% 89.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 1995705 2.73% 92.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1288642 1.76% 94.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 737357 1.01% 95.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 745572 1.02% 96.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2884434 3.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 62672395 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. @@ -44,72 +44,72 @@ system.cpu.commit.COM:loads 19996198 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26497301 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1872416 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56371965 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.965352 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.965352 # CPI: Total CPI of All Threads +system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23336477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30318.337130 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32167.647059 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23335599 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26619500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 878 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 368 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16405500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35388.341031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35272.360069 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493092 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 283496000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001232 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8011 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6278 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 61127000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13298.573785 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29837580 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34887.557656 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29828691 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 310115500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency +system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8889 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6646 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 77532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356524 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1460.322095 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29837580 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34887.557656 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356334 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29828691 # number of overall hits -system.cpu.dcache.overall_miss_latency 310115500 # number of overall miss cycles +system.cpu.dcache.overall_hits 30012251 # number of overall hits +system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8889 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6646 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 77532500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 8940 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -117,280 +117,280 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1460.322095 # Cycle average of tags in use -system.cpu.dcache.total_refs 29828701 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use +system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3982765 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3143444 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162519421 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39357415 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29479520 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8131535 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 48925 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 203223 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31749224 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 838288 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13474 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2813146 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 143267385 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 35496040 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 26313036 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 5601227 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 49112 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 25031 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 32239873 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31371389 # DTB hits -system.cpu.dtb.data_misses 377835 # DTB misses +system.cpu.dtb.data_hits 31883201 # DTB hits +system.cpu.dtb.data_misses 356672 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24565202 # DTB read accesses +system.cpu.dtb.read_accesses 24961741 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24188408 # DTB read hits -system.cpu.dtb.read_misses 376794 # DTB read misses -system.cpu.dtb.write_accesses 7184022 # DTB write accesses +system.cpu.dtb.read_hits 24606273 # DTB read hits +system.cpu.dtb.read_misses 355468 # DTB read misses +system.cpu.dtb.write_accesses 7278132 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7182981 # DTB write hits -system.cpu.dtb.write_misses 1041 # DTB write misses -system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched -system.cpu.fetch.Cycles 30564219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13665829 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.062844 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81154458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.065603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090223 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7276928 # DTB write hits +system.cpu.dtb.write_misses 1204 # DTB write misses +system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched +system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 50590239 62.34% 62.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3137902 3.87% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1890959 2.33% 68.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3231189 3.98% 72.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4367674 5.38% 77.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1502603 1.85% 79.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1888200 2.33% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1658917 2.04% 84.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12886775 15.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 6156758 # number of floating regfile reads -system.cpu.fp_regfile_writes 6040765 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19048295 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 175829000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11152 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1015 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120621000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads +system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1879.086022 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19059447 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15766.588953 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency -system.cpu.icache.demand_hits 19048295 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 175829000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses -system.cpu.icache.demand_misses 11152 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1015 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120621000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency +system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses +system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.756347 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1548.997868 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19059447 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15766.588953 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.755537 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context +system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19048295 # number of overall hits -system.cpu.icache.overall_miss_latency 175829000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses -system.cpu.icache.overall_misses 11152 # number of overall misses -system.cpu.icache.overall_mshr_hits 1015 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120621000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses +system.cpu.icache.overall_hits 17386201 # number of overall hits +system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses +system.cpu.icache.overall_misses 11068 # number of overall misses +system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8219 # number of replacements -system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8218 # number of replacements +system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1548.997868 # Cycle average of tags in use -system.cpu.icache.total_refs 19048295 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use +system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108566 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12934750 # Number of branches executed -system.cpu.iew.EXEC:nop 12801851 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.253335 # Inst execution rate -system.cpu.iew.EXEC:refs 31749416 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7184063 # Number of stores executed +system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12448390 # Number of branches executed +system.cpu.iew.EXEC:nop 11194543 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.455255 # Inst execution rate +system.cpu.iew.EXEC:refs 32240280 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7278167 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91396336 # num instructions consuming a value -system.cpu.iew.WB:count 100051870 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721943 # average fanout of values written-back +system.cpu.iew.WB:consumers 87558338 # num instructions consuming a value +system.cpu.iew.WB:count 97422402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.737743 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65982976 # num instructions producing a value -system.cpu.iew.WB:rate 1.231210 # insts written-back per cycle -system.cpu.iew.WB:sent 100889956 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2057434 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 253528 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33850050 # Number of dispatched load instructions +system.cpu.iew.WB:producers 64595544 # num instructions producing a value +system.cpu.iew.WB:rate 1.424676 # insts written-back per cycle +system.cpu.iew.WB:sent 98290476 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1485832 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10655807 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148273965 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24565353 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2165750 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101849758 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 124164 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 47 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8131535 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 157443 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 842082 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2486 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 1076434 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 268955 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9838 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13853852 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4154704 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 137465323 # number of integer regfile reads -system.cpu.int_regfile_writes 75768353 # number of integer regfile writes -system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 361752 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9740 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 8840023 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2710213 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 134796814 # number of integer regfile reads +system.cpu.int_regfile_writes 73485618 # number of integer regfile writes +system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64603279 62.11% 62.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 474408 0.46% 62.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2788350 2.68% 65.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114559 0.11% 65.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2389553 2.30% 67.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305056 0.29% 67.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755116 0.73% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25265594 24.29% 92.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7319262 7.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104015508 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1951419 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018761 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 101956461 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1618550 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 264504 13.55% 13.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 67 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 1979 0.10% 13.66% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2355 0.12% 13.78% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 826053 42.33% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 56.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 733480 37.59% 93.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 122981 6.30% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81154458 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.281698 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540203 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 68273622 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.493351 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 34964609 43.08% 43.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 18826048 23.20% 66.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 11595868 14.29% 80.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6807186 8.39% 88.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5054639 6.23% 95.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2409288 2.97% 98.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1203500 1.48% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 256390 0.32% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 36930 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate -system.cpu.iq.fp_alu_accesses 8012478 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 15186691 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 7058808 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 12278263 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 97954442 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 276254930 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 92993062 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 174004519 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.490981 # Inst issue rate +system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50629869 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 304728 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47460542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19059519 # ITB accesses +system.cpu.itb.fetch_accesses 17397343 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19059447 # ITB hits -system.cpu.itb.fetch_misses 72 # ITB misses +system.cpu.itb.fetch_hits 17397269 # ITB hits +system.cpu.itb.fetch_misses 74 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -399,105 +399,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34492.672919 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31439.624853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 58844500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.984420 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53636000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984420 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10647 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34284.558824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7247 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116567500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319339 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3400 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105680500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319339 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.091984 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12380 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34354.093224 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7274 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.412439 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5106 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159316500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.412439 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5106 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070256 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2302.164021 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.613547 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12380 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34354.093224 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.070076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7274 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.412439 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5106 # number of overall misses +system.cpu.l2cache.overall_hits 7279 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159316500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.412439 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5106 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3468 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2319.777568 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7255 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17824866 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 712336 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 712206 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 81263024 # number of cpu cycles simulated +system.cpu.numCycles 68382153 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 332303 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40588679 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 939622 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202646679 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157276395 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115514667 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28432140 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 11932541 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 190714138 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 218412469 # The number of ROB reads -system.cpu.rob.rob_writes 304705559 # The number of ROB writes -system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 66062 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 36404617 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 178909439 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 138778599 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 101591818 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25415273 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 5601227 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 515125 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 33164457 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 169177159 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 5077 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1208043 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 457 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 186605606 # The number of ROB reads +system.cpu.rob.rob_writes 260771760 # The number of ROB writes +system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 4743a86c6..40d053507 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -496,7 +496,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 0bb69c5ff..40d08ca97 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:28:39 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 18 2011 20:12:03 +M5 started Mar 18 2011 20:55:41 +M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 129013619500 because target called exit() +122 123 124 Exiting @ tick 124689161500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9ba32bb5a..9197fbb30 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 73857 # Simulator instruction rate (inst/s) -host_mem_usage 259036 # Number of bytes of host memory used -host_seconds 2527.09 # Real time elapsed on the host -host_tick_rate 51052260 # Simulator tick rate (ticks/s) +host_inst_rate 93351 # Simulator instruction rate (inst/s) +host_mem_usage 225124 # Number of bytes of host memory used +host_seconds 2021.07 # Real time elapsed on the host +host_tick_rate 61694693 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 186644197 # Number of instructions simulated -sim_seconds 0.129014 # Number of seconds simulated -sim_ticks 129013619500 # Number of ticks simulated +sim_insts 188669147 # Number of instructions simulated +sim_seconds 0.124689 # Number of seconds simulated +sim_ticks 124689161500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 82595843 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 87704416 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 35994 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 9565909 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 85970608 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 110694771 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 4976778 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 39816389 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1145946 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 82388478 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 87434288 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 36044 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 9641646 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 85843084 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 110166863 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 4949514 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 40244076 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1787959 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 230008327 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.811530 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.187276 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 222534164 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.847886 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.274260 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 121269072 52.72% 52.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 61996527 26.95% 79.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 32262930 14.03% 93.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7261751 3.16% 96.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3043345 1.32% 98.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1671954 0.73% 98.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 847387 0.37% 99.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 509415 0.22% 99.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1145946 0.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 117100961 52.62% 52.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 58370166 26.23% 78.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 31670521 14.23% 93.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 7201653 3.24% 96.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3053342 1.37% 97.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1898242 0.85% 98.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 800122 0.36% 98.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 651198 0.29% 99.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1787959 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 230008327 # Number of insts commited each cycle -system.cpu.commit.COM:count 186658585 # Number of instructions committed -system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1835949 # Number of function calls committed. -system.cpu.commit.COM:int_insts 148665286 # Number of committed integer instructions. -system.cpu.commit.COM:loads 29539429 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 222534164 # Number of insts commited each cycle +system.cpu.commit.COM:count 188683535 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1752310 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1848934 # Number of function calls committed. +system.cpu.commit.COM:int_insts 150271162 # Number of committed integer instructions. +system.cpu.commit.COM:loads 29852012 # Number of loads committed system.cpu.commit.COM:membars 22408 # Number of memory barriers committed -system.cpu.commit.COM:refs 42068801 # Number of memory references committed +system.cpu.commit.COM:refs 42499173 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 9469517 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 186658585 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 1617312 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 187111758 # The number of squashed insts skipped by commit -system.cpu.committedInsts 186644197 # Number of Instructions Simulated -system.cpu.committedInsts_total 186644197 # Number of Instructions Simulated -system.cpu.cpi 1.382455 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.382455 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 26640 # number of LoadLockedReq accesses(hits+misses) +system.cpu.commit.branchMispredicts 9542849 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 188683535 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 1635922 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 177752777 # The number of squashed insts skipped by commit +system.cpu.committedInsts 188669147 # Number of Instructions Simulated +system.cpu.committedInsts_total 188669147 # Number of Instructions Simulated +system.cpu.cpi 1.321776 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.321776 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 26639 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 26638 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits 26637 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000075 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 36653125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33700.747283 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32158.536585 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 36651653 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 49607500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 38457824 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33236.876215 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32051.677852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 38456281 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 51284500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1472 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 734 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23733000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 738 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 24951 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 24951 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 12251566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31103.241534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35107.404022 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 12243977 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 236042500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000619 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7589 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6495 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 38407500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1094 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_misses 1543 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 23878500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 24934 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 24934 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 12364290 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31170.308568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35114.010989 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 12356739 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 235367000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7551 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6459 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 38344500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 26717.914301 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27688.944475 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 48904691 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31525.217967 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33919.486900 # average overall mshr miss latency -system.cpu.dcache.demand_hits 48895630 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 285650000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000185 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9061 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 7229 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 62140500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1832 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 50822114 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31520.947878 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency +system.cpu.dcache.demand_hits 50813020 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 286651500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000179 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9094 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 7257 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 62223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1837 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.340757 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1395.741753 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 48904691 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31525.217967 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33919.486900 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.341673 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1399.491436 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 50822114 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31520.947878 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 48895630 # number of overall hits -system.cpu.dcache.overall_miss_latency 285650000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000185 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9061 # number of overall misses -system.cpu.dcache.overall_mshr_hits 7229 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 62140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1832 # number of overall MSHR misses +system.cpu.dcache.overall_hits 50813020 # number of overall hits +system.cpu.dcache.overall_miss_latency 286651500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000179 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9094 # number of overall misses +system.cpu.dcache.overall_mshr_hits 7257 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 62223000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1837 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 44 # number of replacements -system.cpu.dcache.sampled_refs 1832 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 46 # number of replacements +system.cpu.dcache.sampled_refs 1837 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1395.741753 # Cycle average of tags in use -system.cpu.dcache.total_refs 48947219 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1399.491436 # Cycle average of tags in use +system.cpu.dcache.total_refs 50864591 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 41216121 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 162173 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 17947429 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 450164827 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 82659496 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 104979793 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 27951688 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 694943 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1152916 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:BlockedCycles 36483964 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 165697 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 17673947 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 443458046 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 81104837 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 104098479 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 26775543 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 708476 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 846883 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 110694771 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 38575932 # Number of cache lines fetched -system.cpu.fetch.Cycles 111755859 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1956934 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 439020162 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 55086 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9825072 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.429004 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 38575932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 87572621 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.701449 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 257960014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.834639 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.572532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 110166863 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 38007450 # Number of cache lines fetched +system.cpu.fetch.Cycles 110625948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2015006 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 433901698 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 54587 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9922678 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.441766 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 38007450 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 87337992 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.739933 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 249309706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.873850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.579021 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 146405140 56.75% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4345583 1.68% 58.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33012115 12.80% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15727198 6.10% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9968006 3.86% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16602538 6.44% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8446634 3.27% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5474811 2.12% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17977989 6.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 138852417 55.69% 55.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4190440 1.68% 57.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32866604 13.18% 70.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15794774 6.34% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9866514 3.96% 80.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16440428 6.59% 87.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8394995 3.37% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5405379 2.17% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 17498155 7.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257960014 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2918455 # number of floating regfile reads -system.cpu.fp_regfile_writes 2533041 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 38575932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 23829.127878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20456.359460 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 38571850 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 97270500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000106 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4082 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 71249500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3483 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 249309706 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2867836 # number of floating regfile reads +system.cpu.fp_regfile_writes 2467423 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 38007450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 23681.144866 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20351.582549 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 38003467 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 94322000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000105 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3983 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 71373000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3507 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11074.318117 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10836.460508 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 38575932 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 23829.127878 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20456.359460 # average overall mshr miss latency -system.cpu.icache.demand_hits 38571850 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 97270500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000106 # miss rate for demand accesses -system.cpu.icache.demand_misses 4082 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 71249500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3483 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 38007450 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 23681.144866 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency +system.cpu.icache.demand_hits 38003467 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 94322000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000105 # miss rate for demand accesses +system.cpu.icache.demand_misses 3983 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 71373000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3507 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.621830 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1273.508184 # Average occupied blocks per context -system.cpu.icache.overall_accesses 38575932 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 23829.127878 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20456.359460 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.620951 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1271.708604 # Average occupied blocks per context +system.cpu.icache.overall_accesses 38007450 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 23681.144866 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 38571850 # number of overall hits -system.cpu.icache.overall_miss_latency 97270500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000106 # miss rate for overall accesses -system.cpu.icache.overall_misses 4082 # number of overall misses -system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 71249500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3483 # number of overall MSHR misses +system.cpu.icache.overall_hits 38003467 # number of overall hits +system.cpu.icache.overall_miss_latency 94322000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000105 # miss rate for overall accesses +system.cpu.icache.overall_misses 3983 # number of overall misses +system.cpu.icache.overall_mshr_hits 476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 71373000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3507 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1827 # number of replacements -system.cpu.icache.sampled_refs 3483 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1849 # number of replacements +system.cpu.icache.sampled_refs 3507 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1273.508184 # Cycle average of tags in use -system.cpu.icache.total_refs 38571850 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1271.708604 # Cycle average of tags in use +system.cpu.icache.total_refs 38003467 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 67226 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 52962106 # Number of branches executed -system.cpu.iew.EXEC:nop 84051 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.929014 # Inst execution rate -system.cpu.iew.EXEC:refs 51175949 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 13319638 # Number of stores executed +system.cpu.idleCycles 68618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 53002298 # Number of branches executed +system.cpu.iew.EXEC:nop 82764 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.971537 # Inst execution rate +system.cpu.iew.EXEC:refs 53752491 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 13612548 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285530591 # num instructions consuming a value -system.cpu.iew.WB:count 236209276 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.493714 # average fanout of values written-back +system.cpu.iew.WB:consumers 284939700 # num instructions consuming a value +system.cpu.iew.WB:count 238367932 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.498660 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 140970333 # num instructions producing a value -system.cpu.iew.WB:rate 0.915443 # insts written-back per cycle -system.cpu.iew.WB:sent 237475950 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 10889279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 87073 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 51734063 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2217181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4617225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 19417784 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 373778120 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 37856311 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7515922 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 239710842 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 16182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 142088077 # num instructions producing a value +system.cpu.iew.WB:rate 0.955849 # insts written-back per cycle +system.cpu.iew.WB:sent 239814409 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 10973411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 19948 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 49638370 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2232445 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4819384 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 18009283 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 366444127 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40139943 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7486863 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 242280268 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4512 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11289 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 27951688 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 27726 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2549 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 26775543 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7301 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 619448 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1421 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 948005 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 19233 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 246556 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 22194633 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 6888412 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 246556 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2322193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 8567086 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 532811061 # number of integer regfile reads -system.cpu.int_regfile_writes 228488130 # number of integer regfile writes -system.cpu.ipc 0.723351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.723351 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 222493 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 19786357 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 5362122 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 222493 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2339474 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 8633937 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 541531980 # number of integer regfile reads +system.cpu.int_regfile_writes 230759535 # number of integer regfile writes +system.cpu.ipc 0.756558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.756558 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 192005801 77.66% 77.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 909911 0.37% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7519 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 78.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 33371 0.01% 78.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 78.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 158227 0.06% 78.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 303942 0.12% 78.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 75061 0.03% 78.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 513450 0.21% 78.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 198615 0.08% 78.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 72348 0.03% 78.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 326 0.00% 78.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 39354306 15.92% 94.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 13593887 5.50% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 191948188 76.85% 76.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 913529 0.37% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7217 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32763 0.01% 77.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160980 0.06% 77.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 256110 0.10% 77.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76473 0.03% 77.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 455650 0.18% 77.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202844 0.08% 77.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71631 0.03% 77.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 326 0.00% 77.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 41826421 16.75% 94.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 13815002 5.53% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 247226764 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1255415 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005078 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 249767134 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1600059 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006406 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 17638 1.40% 1.40% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5653 0.45% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1032005 82.20% 84.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 200119 15.94% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 17737 1.11% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 5657 0.35% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.46% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1269103 79.32% 80.78% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 307562 19.22% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 257960014 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.958392 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.149844 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 249309706 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.001835 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200885 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 118566541 45.96% 45.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 70125037 27.18% 73.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 44762596 17.35% 90.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 14438137 5.60% 96.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 6886623 2.67% 98.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2484508 0.96% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 597059 0.23% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 85366 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 14147 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 113103229 45.37% 45.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 65846302 26.41% 71.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 43653759 17.51% 89.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 15345322 6.16% 95.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 7500866 3.01% 98.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2857086 1.15% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 799949 0.32% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 136784 0.05% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 66409 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 257960014 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.958142 # Inst issue rate -system.cpu.iq.fp_alu_accesses 1985429 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 3952184 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 1885790 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 3082571 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 246496750 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 750098950 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 234323486 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 555603223 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 371452773 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 247226764 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2241296 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 184786827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 382177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 623984 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 306361873 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 249309706 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.001559 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1880181 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3740694 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1822482 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2256352 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 249487012 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 746951727 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 236545450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 539735109 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 364104789 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 249767134 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2256574 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 175408140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 248391 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 620652 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 277084807 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,106 +416,106 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34292.357274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31035.911602 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_accesses 1092 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34297.509225 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.822878 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 37241500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.992687 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1086 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33705000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992687 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1086 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4221 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34284.967067 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.317225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1640 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 88489500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.611466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_miss_latency 37178500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.992674 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1084 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992674 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1084 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34293.776575 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31074.261275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 88718000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.608420 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2587 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 79729000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607913 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2566 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 79923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.604892 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2572 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.637141 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.645349 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 5315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34287.155713 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31060.788609 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1648 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 125731000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.689934 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3667 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 5344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34294.878780 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1673 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 125896500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.686939 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3671 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 113434000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.687112 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3652 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 113568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.684132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3656 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.056054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.056059 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1836.784505 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.029906 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 5315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34287.155713 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31060.788609 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1836.948830 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.029636 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 5344 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34294.878780 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1648 # number of overall hits -system.cpu.l2cache.overall_miss_latency 125731000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.689934 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3667 # number of overall misses +system.cpu.l2cache.overall_hits 1673 # number of overall hits +system.cpu.l2cache.overall_miss_latency 125896500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.686939 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3671 # number of overall misses system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 113434000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.687112 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3652 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 113568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.684132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3656 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2574 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2580 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1839.814411 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1640 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1839.978467 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1665 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 20836418 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10554028 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 51734063 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 19417784 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 525439504 # number of misc regfile reads -system.cpu.misc_regfile_writes 4891826 # number of misc regfile writes -system.cpu.numCycles 258027240 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 5431209 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4203967 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 49638370 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18009283 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 520185841 # number of misc regfile reads +system.cpu.misc_regfile_writes 4959640 # number of misc regfile writes +system.cpu.numCycles 249378324 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2330030 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 180535361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 944198 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 91504327 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3682942 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 971479303 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 419602585 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 423243474 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 97150161 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 27951688 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7290618 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 242708110 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 16446952 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 955032351 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 31733190 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2646445 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 27810547 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2436395 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 602627523 # The number of ROB reads -system.cpu.rob.rob_writes 775494029 # The number of ROB writes -system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 894474 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 182569794 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 613304 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 89635884 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2121775 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 950994709 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 412692464 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 417292399 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 96328320 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 26775543 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5285061 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 234722601 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 13811231 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 937183478 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 30390424 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2644938 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 23801477 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2441234 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 587177316 # The number of ROB reads +system.cpu.rob.rob_writes 759649734 # The number of ROB writes +system.cpu.timesIdled 1415 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index f69fd4da6..61dc4a8fe 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 @@ -488,7 +491,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 2ac976df6..d11a4f41f 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 12 2011 02:22:23 -M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch -M5 started Feb 12 2011 02:22:27 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +M5 compiled Mar 18 2011 20:12:06 +M5 started Mar 18 2011 20:12:16 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 108875474000 because target called exit() +122 123 124 Exiting @ tick 106785381000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index a77afc849..4edd15028 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 92938 # Simulator instruction rate (inst/s) -host_mem_usage 245208 # Number of bytes of host memory used -host_seconds 2381.84 # Real time elapsed on the host -host_tick_rate 45710653 # Simulator tick rate (ticks/s) +host_inst_rate 118324 # Simulator instruction rate (inst/s) +host_mem_usage 224536 # Number of bytes of host memory used +host_seconds 1870.83 # Real time elapsed on the host +host_tick_rate 57079180 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.108875 # Number of seconds simulated -sim_ticks 108875474000 # Number of ticks simulated +sim_seconds 0.106785 # Number of seconds simulated +sim_ticks 106785381000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19602584 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 22433110 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3071588 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2318001 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 190318905 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.163116 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 190318905 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,424 +44,430 @@ system.cpu.commit.COM:loads 56649590 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.964799 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50490336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33183.118741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34227.979275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50489637 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 23195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 699 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 13212000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 386 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 26460.898971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.187380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 187793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5528 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55659000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36353.441884 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency -system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses -system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 71006066 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 27063.622370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency +system.cpu.dcache.demand_hits 70998270 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 210988000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7796 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5841 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68871000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.341442 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 71003033 # number of overall hits -system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000109 # miss rate for overall accesses -system.cpu.dcache.overall_misses 7734 # number of overall misses -system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 68562500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses +system.cpu.dcache.overall_hits 70998270 # number of overall hits +system.cpu.dcache.overall_miss_latency 210988000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7796 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5841 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68871000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 1953 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use -system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1398.546932 # Cycle average of tags in use +system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched -system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 57112679 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 420105654 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 67048451 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 60385094 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 23161998 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 5772681 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched +system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 448608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 261554963 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3099299 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117410 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27531173 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 19602584 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.224676 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 213480903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.014170 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.226415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 145760613 68.28% 68.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3769966 1.77% 70.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3155448 1.48% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4279066 2.00% 73.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4652490 2.18% 75.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4411215 2.07% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5002306 2.34% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3209548 1.50% 81.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39240251 18.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads -system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 213480903 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3511578 # number of floating regfile reads +system.cpu.fp_regfile_writes 2187329 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 27531173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25557.221784 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22462.481426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 27524838 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 161905000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 6335 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 951 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 5384 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5114.239688 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency -system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses -system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 27531173 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25557.221784 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency +system.cpu.icache.demand_hits 27524838 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 161905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses +system.cpu.icache.demand_misses 6335 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 951 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 5384 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context -system.cpu.icache.overall_accesses 27858568 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.784044 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context +system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 27852177 # number of overall hits -system.cpu.icache.overall_miss_latency 163077000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000229 # miss rate for overall accesses -system.cpu.icache.overall_misses 6391 # number of overall misses -system.cpu.icache.overall_mshr_hits 1005 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses +system.cpu.icache.overall_hits 27524838 # number of overall hits +system.cpu.icache.overall_miss_latency 161905000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses +system.cpu.icache.overall_misses 6335 # number of overall misses +system.cpu.icache.overall_mshr_hits 951 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 5384 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3428 # number of replacements -system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3426 # number of replacements +system.cpu.icache.sampled_refs 5382 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use -system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1605.721886 # Cycle average of tags in use +system.cpu.icache.total_refs 27524838 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 15799905 # Number of branches executed +system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 15858881 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate -system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 22888685 # Number of stores executed +system.cpu.iew.EXEC:rate 1.303230 # Inst execution rate +system.cpu.iew.EXEC:refs 90240962 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 23196856 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value -system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back +system.cpu.iew.WB:consumers 371845968 # num instructions consuming a value +system.cpu.iew.WB:count 275965139 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.599241 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 223241922 # num instructions producing a value -system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle -system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 222825226 # num instructions producing a value +system.cpu.iew.WB:rate 1.292148 # insts written-back per cycle +system.cpu.iew.WB:sent 277010234 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 231101 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 37116725 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 395719031 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 67044106 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3514925 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 278331746 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 453294 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 16343714 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 514946932 # number of integer regfile reads -system.cpu.int_regfile_writes 284476955 # number of integer regfile writes -system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1195391 0.42% 0.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 187555358 66.63% 67.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589850 0.56% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 67998663 24.16% 91.77% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 23168272 8.23% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 35659 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 45746 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 48346210 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 16601009 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 516469209 # number of integer regfile reads +system.cpu.int_regfile_writes 283974364 # number of integer regfile writes +system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 281846671 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 2813875 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2334735 84.00% 86.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 386272 13.90% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 217661766 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 213480903 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.320243 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 37681009 17.31% 82.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate -system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2526643 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency +system.cpu.iq.ISSUE:issued_per_cycle::total 213480903 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.319688 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 564126820 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 395717604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 281846671 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1427 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 174039946 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 53929500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996171 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1561 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48940000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996171 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1561 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5768 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34292.872747 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.872747 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2106 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 125580500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.634882 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 113679000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634882 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.574468 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34369.136512 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2112 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179510000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.712065 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5223 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 162619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.712065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5223 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.074157 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2116 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5220 # number of overall misses +system.cpu.l2cache.overall_hits 2112 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179510000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.712065 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5223 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 162619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.712065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2431.000786 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2106 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 90499072 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30541649 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 104995800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37116725 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 145140832 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 217750949 # number of cpu cycles simulated +system.cpu.numCycles 213570763 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 18060003 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 592991425 # The number of ROB reads -system.cpu.rob.rob_writes 827053987 # The number of ROB writes -system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 21564374 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 74887260 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 1054491347 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 409882715 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 430914543 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 57380379 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 23161998 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39968831 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 196551134 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 11087102 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1043404245 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 22432 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1444 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 83221554 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 1312 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 583734688 # The number of ROB reads +system.cpu.rob.rob_writes 814640460 # The number of ROB writes +system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- |