diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/70.twolf/ref | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/70.twolf/ref')
15 files changed, 614 insertions, 663 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 72f88064b..107f17441 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 78d80c7fd..b14e624c0 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:18:42 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:52:34 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 98337080000 because target called exit() +122 123 124 Exiting @ tick 98335161000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 4e98786e0..3c9f3dbf4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 33745 # Simulator instruction rate (inst/s) -host_mem_usage 211108 # Number of bytes of host memory used -host_seconds 2723.45 # Real time elapsed on the host -host_tick_rate 36107563 # Simulator tick rate (ticks/s) +host_inst_rate 54763 # Simulator instruction rate (inst/s) +host_mem_usage 197304 # Number of bytes of host memory used +host_seconds 1678.20 # Real time elapsed on the host +host_tick_rate 58595727 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098337 # Number of seconds simulated -sim_ticks 98337080000 # Number of ticks simulated +sim_seconds 0.098335 # Number of seconds simulated +sim_ticks 98335161000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064 system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 185972268 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 95.460360 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 95.462227 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43625545 # Number of Integer instructions committed @@ -42,28 +42,28 @@ system.cpu.comStores 6502695 # Nu system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads +system.cpu.cpi 2.139976 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.139976 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48524.210526 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23049000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55595.537757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52592.105263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 97181000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 91931000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54730.994152 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 121667000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114980000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352016 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.857733 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54730.994152 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495062 # number of overall hits -system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles +system.cpu.dcache.overall_hits 26495078 # number of overall hits +system.cpu.dcache.overall_miss_latency 121667000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2239 # number of overall misses +system.cpu.dcache.overall_misses 2223 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114980000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.857733 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.dcache.writebacks 107 # number of writebacks system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 26497301 # DTB hits @@ -126,50 +126,50 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_avg_miss_latency 27216.197508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.134662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 101754083 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 235910000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205719500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 8668 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205720500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8577 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2000 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11863.598578 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 11863.598344 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency -system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_avg_miss_latency 27216.197508 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency +system.cpu.icache.demand_hits 101754083 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 235910000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205719500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 8668 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205720500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8577 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.697636 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.759296 # Average occupied blocks per context system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 27216.197508 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 101754085 # number of overall hits -system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles +system.cpu.icache.overall_hits 101754083 # number of overall hits +system.cpu.icache.overall_miss_latency 235910000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8666 # number of overall misses -system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205719500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 8668 # number of overall misses +system.cpu.icache.overall_mshr_hits 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205720500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8577 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6743 # number of replacements system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use -system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.759296 # Cycle average of tags in use +system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads +system.cpu.idleCycles 8924453 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,104 +201,96 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.318235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.807201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89916500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68890000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52167.972576 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 159790500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.916906 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 52185.370951 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6015 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 249707000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443056 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4785 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 191471500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4785 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.063286 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2073.767582 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.791341 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52185.370951 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5989 # number of overall hits -system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4811 # number of overall misses +system.cpu.l2cache.overall_hits 6015 # number of overall hits +system.cpu.l2cache.overall_miss_latency 249707000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.443056 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4785 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 191471500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.443056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4785 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3129 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2091.558923 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5998 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 196674161 # number of cpu cycles simulated -system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed. +system.cpu.numCycles 196670323 # number of cpu cycles simulated +system.cpu.runCycles 187745870 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94907524 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 51.742834 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 104509809 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 46.860407 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 170133192 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.493206 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 196670323 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d1980c8dc..bcd7db1f0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 9e4298349..64c5673b1 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:11:51 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:34:48 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 40700936000 because target called exit() +122 123 124 Exiting @ tick 40701237000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 88a37a0c5..434f6f061 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,295 +1,295 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 126678 # Simulator instruction rate (inst/s) -host_mem_usage 211676 # Number of bytes of host memory used -host_seconds 664.52 # Real time elapsed on the host -host_tick_rate 61249065 # Simulator tick rate (ticks/s) +host_inst_rate 172806 # Simulator instruction rate (inst/s) +host_mem_usage 197872 # Number of bytes of host memory used +host_seconds 487.13 # Real time elapsed on the host +host_tick_rate 83552440 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040701 # Number of seconds simulated -sim_ticks 40700936000 # Number of ticks simulated +sim_ticks 40701237000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 11915731 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15874516 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11915545 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15874334 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1889856 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14601933 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19578482 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 1889899 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14602096 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19578655 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2865019 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2864912 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73200115 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.255504 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.951469 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 73200571 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.255496 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.951465 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 35882998 49.02% 49.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 18421131 25.17% 74.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 7399939 10.11% 84.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3793003 5.18% 89.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2033143 2.78% 92.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1324637 1.81% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 734587 1.00% 95.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 745658 1.02% 96.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2865019 3.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 35883667 49.02% 49.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 18420857 25.16% 74.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 7399798 10.11% 84.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3793136 5.18% 89.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2033346 2.78% 92.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1324316 1.81% 94.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 734839 1.00% 95.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 745700 1.02% 96.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2864912 3.91% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73200115 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 73200571 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1876719 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1876760 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56257070 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 56257975 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.967001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.967001 # CPI: Total CPI of All Threads +system.cpu.cpi 0.967008 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.967008 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23361768 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30148.648649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32165.686275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23360880 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26772000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 23361980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30151.634724 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32163.725490 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23361093 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26744500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 888 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16404500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 887 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 377 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16403500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35665.614165 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35983.686319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493027 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 288035500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8076 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6329 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 62863500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1747 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 35569.269207 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35483.256351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493098 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 284732000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001231 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8005 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6273 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 61457000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13315.768510 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13315.879572 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29862871 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35119.087461 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29853907 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 314807500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000300 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8964 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6707 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 79268000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2257 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29863083 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35028.846154 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29854191 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 311476500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses +system.cpu.dcache.demand_misses 8892 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6650 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 77860500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356506 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1460.250343 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29862871 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35119.087461 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356508 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1460.254824 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29863083 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35028.846154 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29853907 # number of overall hits -system.cpu.dcache.overall_miss_latency 314807500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000300 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8964 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6707 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 79268000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2257 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29854191 # number of overall hits +system.cpu.dcache.overall_miss_latency 311476500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses +system.cpu.dcache.overall_misses 8892 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6650 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 77860500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1460.250343 # Cycle average of tags in use -system.cpu.dcache.total_refs 29853953 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1460.254824 # Cycle average of tags in use +system.cpu.dcache.total_refs 29854202 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4195548 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13275 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3138319 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162326104 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39347421 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29437279 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8092915 # Number of cycles decode is squashing +system.cpu.dcache.writebacks 109 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 4195761 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13279 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3138343 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162326891 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39347906 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29437041 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8093015 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 219867 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31798312 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 219863 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31798533 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31419824 # DTB hits -system.cpu.dtb.data_misses 378488 # DTB misses +system.cpu.dtb.data_hits 31420024 # DTB hits +system.cpu.dtb.data_misses 378509 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24587008 # DTB read accesses +system.cpu.dtb.read_accesses 24587243 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24209579 # DTB read hits -system.cpu.dtb.read_misses 377429 # DTB read misses -system.cpu.dtb.write_accesses 7211304 # DTB write accesses +system.cpu.dtb.read_hits 24209793 # DTB read hits +system.cpu.dtb.read_misses 377450 # DTB read misses +system.cpu.dtb.write_accesses 7211290 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7210245 # DTB write hits +system.cpu.dtb.write_hits 7210231 # DTB write hits system.cpu.dtb.write_misses 1059 # DTB write misses -system.cpu.fetch.Branches 19578482 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19042269 # Number of cache lines fetched -system.cpu.fetch.Cycles 49581999 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 482446 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167417229 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2029251 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240516 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19042269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13652580 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.056675 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81293030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.087442 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 19578655 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19042384 # Number of cache lines fetched +system.cpu.fetch.Cycles 49581925 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 482421 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167418269 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2029286 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.240517 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19042384 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13652394 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.056673 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 81293586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.087450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 50753371 62.43% 62.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3139837 3.86% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1896166 2.33% 68.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3230989 3.97% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4381492 5.39% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1498123 1.84% 79.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1855484 2.28% 82.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1657938 2.04% 84.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12879630 15.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 50754116 62.43% 62.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3139628 3.86% 66.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1895979 2.33% 68.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3231029 3.97% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4381369 5.39% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1498108 1.84% 79.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1855702 2.28% 82.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1657872 2.04% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12879783 15.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81293030 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19042269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15754.189443 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11879.245840 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19031110 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 175801000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 81293586 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19042384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15742.896836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11872.070120 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19031227 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175643500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11159 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1002 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120657500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 11157 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120549000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10157 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 10154 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1873.694004 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1874.259110 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19042269 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15754.189443 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency -system.cpu.icache.demand_hits 19031110 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 175801000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 19042384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15742.896836 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency +system.cpu.icache.demand_hits 19031227 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175643500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses -system.cpu.icache.demand_misses 11159 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1002 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120657500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 11157 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120549000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10157 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10154 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.756087 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1548.466977 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19042269 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15754.189443 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.756089 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1548.470149 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19042384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15742.896836 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19031110 # number of overall hits -system.cpu.icache.overall_miss_latency 175801000 # number of overall miss cycles +system.cpu.icache.overall_hits 19031227 # number of overall hits +system.cpu.icache.overall_miss_latency 175643500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses -system.cpu.icache.overall_misses 11159 # number of overall misses -system.cpu.icache.overall_mshr_hits 1002 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120657500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 11157 # number of overall misses +system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120549000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10157 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10154 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8241 # number of replacements -system.cpu.icache.sampled_refs 10157 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8238 # number of replacements +system.cpu.icache.sampled_refs 10154 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1548.466977 # Cycle average of tags in use -system.cpu.icache.total_refs 19031110 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1548.470149 # Cycle average of tags in use +system.cpu.icache.total_refs 19031227 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12932923 # Number of branches executed -system.cpu.iew.EXEC:nop 12752202 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.252024 # Inst execution rate -system.cpu.iew.EXEC:refs 31851727 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7212953 # Number of stores executed +system.cpu.idleCycles 108889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12932789 # Number of branches executed +system.cpu.iew.EXEC:nop 12752151 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.252018 # Inst execution rate +system.cpu.iew.EXEC:refs 31851951 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7212939 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91350917 # num instructions consuming a value -system.cpu.iew.WB:count 100121723 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.722506 # average fanout of values written-back +system.cpu.iew.WB:consumers 91351431 # num instructions consuming a value +system.cpu.iew.WB:count 100121785 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.722504 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 66001625 # num instructions producing a value -system.cpu.iew.WB:rate 1.229968 # insts written-back per cycle -system.cpu.iew.WB:sent 100959925 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2058548 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 308035 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33906352 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 439 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1495689 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10659868 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148158966 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24638774 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2167496 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101917138 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 147063 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 66001783 # num instructions producing a value +system.cpu.iew.WB:rate 1.229960 # insts written-back per cycle +system.cpu.iew.WB:sent 100960101 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2058583 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 308073 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33906754 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1495766 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10659940 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148159865 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24639012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2167407 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101917357 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 147057 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8092915 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 184741 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 229 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8093015 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 184742 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 837967 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 837974 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2531 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 262394 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13871939 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4157173 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 262394 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 456488 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1602060 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.034125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.034125 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 262379 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13872341 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4157245 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 262379 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 456408 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1602175 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.034117 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.034117 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580885 62.05% 62.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 474250 0.46% 62.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580956 62.05% 62.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474234 0.46% 62.50% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786793 2.68% 65.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786797 2.68% 65.18% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387015 2.29% 67.58% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387018 2.29% 67.58% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25334190 24.34% 92.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346496 7.06% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25334340 24.34% 92.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346414 7.06% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104084634 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1605159 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015422 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 104084764 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1605421 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015424 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 233517 14.55% 14.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 233590 14.55% 14.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available @@ -298,42 +298,42 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # at system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 750460 46.75% 95.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 76517 4.77% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 750644 46.76% 95.23% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 76522 4.77% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81293030 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280364 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539599 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 81293586 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280356 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539590 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 34992329 43.04% 43.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 18915944 23.27% 66.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 11753054 14.46% 80.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6613669 8.14% 88.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5112903 6.29% 95.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2406334 2.96% 98.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1201307 1.48% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 249469 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 48021 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 34992440 43.04% 43.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 18916491 23.27% 66.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 11753286 14.46% 80.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6613191 8.13% 88.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5113111 6.29% 95.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2406044 2.96% 98.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1201508 1.48% 99.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 249704 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 47811 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81293030 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.278652 # Inst issue rate -system.cpu.iq.iqInstsAdded 135406325 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104084634 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 439 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50573904 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 302099 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47258027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 81293586 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.278644 # Inst issue rate +system.cpu.iq.iqInstsAdded 135407278 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104084764 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50574577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 302079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47259225 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19042340 # ITB accesses +system.cpu.itb.fetch_accesses 19042455 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19042269 # ITB hits +system.cpu.itb.fetch_hits 19042384 # ITB hits system.cpu.itb.fetch_misses 71 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,103 +344,95 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34688.510393 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31520.207852 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60080500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1732 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54593000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1732 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10667 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34283.465725 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.788761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34699.413490 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31528.152493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 59162500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.984411 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1705 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53755500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10664 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.213192 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.566549 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116529500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.318646 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3399 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105647000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318646 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3399 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 512500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 465000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.ReadReq_miss_latency 116419000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318455 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3396 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105553000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318455 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3396 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.094427 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.100462 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12399 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34420.190996 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7268 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 176610000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413824 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5131 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12396 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34420.995883 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7295 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175581500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411504 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5101 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 160240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5131 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159308500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411504 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5101 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2302.538330 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.547355 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12399 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34420.190996 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency +system.cpu.l2cache.occ_%::1 0.000537 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2302.534301 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.609654 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12396 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34420.995883 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7268 # number of overall hits -system.cpu.l2cache.overall_miss_latency 176610000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.413824 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5131 # number of overall misses +system.cpu.l2cache.overall_hits 7295 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175581500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411504 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5101 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 160240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.413824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5131 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159308500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411504 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3463 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3464 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2316.085685 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7253 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2320.143954 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17615087 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5052814 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33906352 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10659868 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 81401873 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1958439 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17616969 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5053323 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33906754 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10659940 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 81402475 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1958550 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1204670 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40603212 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 943778 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202469078 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157094553 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115390079 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28386104 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8092915 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2247194 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 46962718 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5166 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 474 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4950472 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IQFullEvents 1204707 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40603552 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 943829 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202471233 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157096154 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115391431 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28385991 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8093015 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2247276 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 46964070 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5202 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 471 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4950569 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 460 # count of temporary serializing insts renamed system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 3a1e6de05..81bd24631 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 258e66688..638d6c514 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:58:58 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:04:52 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -30,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118742021000 because target called exit() +122 123 124 Exiting @ tick 118740049000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b08531811..fb91662b2 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1269659 # Simulator instruction rate (inst/s) -host_mem_usage 210612 # Number of bytes of host memory used -host_seconds 72.38 # Real time elapsed on the host -host_tick_rate 1640438984 # Simulator tick rate (ticks/s) +host_inst_rate 1097596 # Simulator instruction rate (inst/s) +host_mem_usage 196804 # Number of bytes of host memory used +host_seconds 83.73 # Real time elapsed on the host +host_tick_rate 1418103765 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118742 # Number of seconds simulated -sim_ticks 118742021000 # Number of ticks simulated +sim_seconds 0.118740 # Number of seconds simulated +sim_ticks 118740049000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 98784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 93492000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55005.806163 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123158000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 116441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352059 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1442.035674 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55005.806163 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495062 # number of overall hits -system.cpu.dcache.overall_miss_latency 123158000 # number of overall miss cycles +system.cpu.dcache.overall_hits 26495078 # number of overall hits +system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2239 # number of overall misses +system.cpu.dcache.overall_misses 2223 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 116441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1442.035674 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.dcache.writebacks 107 # number of writebacks system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 26497301 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692403 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1418.041181 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.041181 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,12 +164,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -180,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses 3043 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 832000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 640000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.909179 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2056.260143 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.724287 # Average occupied blocks per context +system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4791 # number of overall misses +system.cpu.l2cache.overall_hits 5968 # number of overall hits +system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4765 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3105 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2069.984431 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237484042 # number of cpu cycles simulated +system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index 43ac38afd..efc2b1daf 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index a3b84a071..931f30561 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:54:23 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:05:16 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -30,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232028062000 because target called exit() +122 123 124 Exiting @ tick 232027671000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 156b8dc2a..ea6f10d3a 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1713926 # Simulator instruction rate (inst/s) -host_mem_usage 214560 # Number of bytes of host memory used -host_seconds 108.72 # Real time elapsed on the host -host_tick_rate 2134224518 # Simulator tick rate (ticks/s) +host_inst_rate 1260082 # Simulator instruction rate (inst/s) +host_mem_usage 200384 # Number of bytes of host memory used +host_seconds 147.87 # Real time elapsed on the host +host_tick_rate 1569082964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186333855 # Number of instructions simulated sim_seconds 0.232028 # Number of seconds simulated -sim_ticks 232028062000 # Number of ticks simulated +sim_ticks 232027671000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 34134000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 690 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 12385593 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 12385594 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54639.865997 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency -system.cpu.dcache.demand_hits 42025083 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97860000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54451.396648 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency +system.cpu.dcache.demand_hits 42025084 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97468000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1791 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1790 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 92487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 92098000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1791 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1790 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.333155 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1364.601520 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 1364.601667 # Average occupied blocks per context system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54639.865997 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54451.396648 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 42025083 # number of overall hits -system.cpu.dcache.overall_miss_latency 97860000 # number of overall miss cycles +system.cpu.dcache.overall_hits 42025084 # number of overall hits +system.cpu.dcache.overall_miss_latency 97468000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1791 # number of overall misses +system.cpu.dcache.overall_misses 1790 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 92487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 92098000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1791 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1790 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1364.601520 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1364.601667 # Cycle average of tags in use system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks @@ -115,7 +115,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.560536 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1147.977742 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1147.977892 # Average occupied blocks per context system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1506 # number of replacements system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1147.977742 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.977892 # Cycle average of tags in use system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 57200000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1100 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 44000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1100 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 3741 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -166,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses 2361 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 52000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 40000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.582348 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 4841 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1380 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.714935 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3461 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1388 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.713282 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 138440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.714935 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.713282 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1672.604273 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2.043764 # Average occupied blocks per context +system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1672.604511 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.037968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1380 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179972000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.714935 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3461 # number of overall misses +system.cpu.l2cache.overall_hits 1388 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.713282 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3453 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 138440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.714935 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.713282 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2368 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1674.648036 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1675.642479 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 464056124 # number of cpu cycles simulated +system.cpu.numCycles 464055342 # number of cpu cycles simulated system.cpu.num_insts 186333855 # Number of instructions executed system.cpu.num_refs 42511846 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index c1e1fc55b..8e0eaa820 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 705b33507..f2c1160f5 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:20:12 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:26:25 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:26:56 +M5 executing on phenom command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -31,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250960757000 because target called exit() +122 123 124 Exiting @ tick 250960631000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 24bf72eb4..69e591ac8 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 935562 # Simulator instruction rate (inst/s) -host_mem_usage 217504 # Number of bytes of host memory used -host_seconds 234.54 # Real time elapsed on the host -host_tick_rate 1069990696 # Simulator tick rate (ticks/s) +host_inst_rate 1231791 # Simulator instruction rate (inst/s) +host_mem_usage 202836 # Number of bytes of host memory used +host_seconds 178.14 # Real time elapsed on the host +host_tick_rate 1408783027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 219431024 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated -sim_ticks 250960757000 # Number of ticks simulated +sim_ticks 250960631000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency @@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 88368000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 83634000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55846.719160 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 106388000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 100672500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1363.451646 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55846.719160 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.overall_miss_latency 106388000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 1905 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100672500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -69,7 +69,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1363.451646 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 7 # number of writebacks @@ -106,7 +106,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1455.289171 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2836 # number of replacements system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.289171 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -132,12 +132,13 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 82056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -159,46 +160,46 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52003.271423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1861 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246391500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.717988 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4738 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 189520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.717988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4738 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2058.146657 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021757 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1861 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246391500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.717988 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4738 # number of overall misses +system.cpu.l2cache.overall_hits 1864 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4735 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.717988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4738 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2058.168414 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501921514 # number of cpu cycles simulated +system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.num_insts 219431024 # Number of instructions executed system.cpu.num_refs 77165306 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |