diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:27 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:27 -0500 |
| commit | 307f089e7f67d4a314e95a3f53b721e0971e2183 (patch) | |
| tree | 13b97a21d77ed2acafea141345ca5b3fb27ff50d /tests/long/70.twolf/ref | |
| parent | 8aff996db13d039e3021671718b55e3c56b1c95d (diff) | |
| download | gem5-307f089e7f67d4a314e95a3f53b721e0971e2183.tar.xz | |
O3/ARM: Update stats for recent changes.
Diffstat (limited to 'tests/long/70.twolf/ref')
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 669 |
3 files changed, 340 insertions, 339 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 15faea73a..98cead180 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 5be7bed53..1b4fcdc8a 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 13:30:37 -M5 started Apr 21 2011 13:53:57 -M5 executing on maize +M5 compiled May 1 2011 16:48:51 +M5 started May 1 2011 16:48:54 +M5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -28,4 +28,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 106785381000 because target called exit() +122 123 124 Exiting @ tick 106659390000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index e5f49060a..176877f02 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 120975 # Simulator instruction rate (inst/s) -host_mem_usage 223752 # Number of bytes of host memory used -host_seconds 1829.83 # Real time elapsed on the host -host_tick_rate 58358040 # Simulator tick rate (ticks/s) +host_inst_rate 88999 # Simulator instruction rate (inst/s) +host_mem_usage 265284 # Number of bytes of host memory used +host_seconds 2487.25 # Real time elapsed on the host +host_tick_rate 42882469 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.106785 # Number of seconds simulated -sim_ticks 106785381000 # Number of ticks simulated +sim_seconds 0.106659 # Number of seconds simulated +sim_ticks 106659390000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 19602584 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 22433110 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19559071 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 22388883 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3071588 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3071862 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 25034838 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 25034838 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3071894 # The number of times a branch was mispredicted system.cpu.commit.branches 12326943 # Number of branches committed -system.cpu.commit.bw_lim_events 2318001 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2350531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 190318905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.163116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 173965235 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 190108496 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.164404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.519902 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74006380 38.93% 38.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 71095556 37.40% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18250817 9.60% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12666090 6.66% 92.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5885570 3.10% 95.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2802504 1.47% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1948827 1.03% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1102221 0.58% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2350531 1.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 190318905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 190108496 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. @@ -50,337 +50,337 @@ system.cpu.commit.refs 77165306 # Nu system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964799 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 50490336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33183.118741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34227.979275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 50489637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 23195000 # number of ReadReq miss cycles +system.cpu.cpi 0.963660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.963660 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50560876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50560179 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 23121000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 699 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 13212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 697 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 310 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 13246500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 386 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 387 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26460.898971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.187380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 187793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 187990000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5528 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55659000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 5527 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55693000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1570 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 36353.441884 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36352.334527 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 71006066 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27063.622370 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency -system.cpu.dcache.demand_hits 70998270 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 210988000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 71076606 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 27086.348473 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency +system.cpu.dcache.demand_hits 71068812 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 211111000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses -system.cpu.dcache.demand_misses 7796 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 5841 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 68871000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 7794 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5837 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68939500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1955 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.341442 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 1400.398145 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.341894 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 71076606 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 27086.348473 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 70998270 # number of overall hits -system.cpu.dcache.overall_miss_latency 210988000 # number of overall miss cycles +system.cpu.dcache.overall_hits 71068812 # number of overall hits +system.cpu.dcache.overall_miss_latency 211111000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses -system.cpu.dcache.overall_misses 7796 # number of overall misses -system.cpu.dcache.overall_mshr_hits 5841 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 68871000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 7794 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5837 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68939500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1955 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.sampled_refs 1953 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1398.546932 # Cycle average of tags in use -system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1400.398145 # Cycle average of tags in use +system.cpu.dcache.total_refs 71068814 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.decode.BlockedCycles 57112679 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 420105654 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 67048451 # Number of cycles decode is idle -system.cpu.decode.RunCycles 60385094 # Number of cycles decode is running -system.cpu.decode.SquashCycles 23161998 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 5772681 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched -system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 448608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 261554963 # Number of instructions fetch has processed +system.cpu.decode.BlockedCycles 57002752 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 419872535 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 66995296 # Number of cycles decode is idle +system.cpu.decode.RunCycles 60323444 # Number of cycles decode is running +system.cpu.decode.SquashCycles 23120513 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 5787004 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 25034838 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 27511716 # Number of cache lines fetched +system.cpu.fetch.Cycles 69512577 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 449654 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 261443886 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3099299 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.117410 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 27531173 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 19602584 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.224676 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 213480903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.014170 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.226415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 3099669 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117359 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27511716 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 19559071 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.225602 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 213229009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.015146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.226933 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 145760613 68.28% 68.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3769966 1.77% 70.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3155448 1.48% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4279066 2.00% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4652490 2.18% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4411215 2.07% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5002306 2.34% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3209548 1.50% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39240251 18.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 145563800 68.27% 68.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3763912 1.77% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3143749 1.47% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4274487 2.00% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4655568 2.18% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4407393 2.07% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4998818 2.34% 80.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3209647 1.51% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39211635 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 213480903 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3511578 # number of floating regfile reads -system.cpu.fp_regfile_writes 2187329 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 27531173 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25557.221784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22462.481426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 27524838 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 161905000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 213229009 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3514377 # number of floating regfile reads +system.cpu.fp_regfile_writes 2187528 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 27511716 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25569.940006 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 27505382 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 161960000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6335 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 6334 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 952 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120905500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 5382 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5114.239688 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5112.524535 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 27531173 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25557.221784 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency -system.cpu.icache.demand_hits 27524838 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 161905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 27511716 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25569.940006 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency +system.cpu.icache.demand_hits 27505382 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 161960000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.icache.demand_misses 6335 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 6334 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 952 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120905500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 5382 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.784044 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1605.599338 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.783984 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 27511716 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25569.940006 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 27524838 # number of overall hits -system.cpu.icache.overall_miss_latency 161905000 # number of overall miss cycles +system.cpu.icache.overall_hits 27505382 # number of overall hits +system.cpu.icache.overall_miss_latency 161960000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.icache.overall_misses 6335 # number of overall misses -system.cpu.icache.overall_mshr_hits 951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 6334 # number of overall misses +system.cpu.icache.overall_mshr_hits 952 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120905500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 5382 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3426 # number of replacements -system.cpu.icache.sampled_refs 5382 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3421 # number of replacements +system.cpu.icache.sampled_refs 5380 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1605.721886 # Cycle average of tags in use -system.cpu.icache.total_refs 27524838 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1605.599338 # Cycle average of tags in use +system.cpu.icache.total_refs 27505382 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 15858881 # Number of branches executed +system.cpu.idleCycles 89772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3285583 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 15876599 # Number of branches executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 1.303230 # Inst execution rate -system.cpu.iew.exec_refs 90240962 # number of memory reference insts executed -system.cpu.iew.exec_stores 23196856 # Number of stores executed +system.cpu.iew.exec_rate 1.304758 # Inst execution rate +system.cpu.iew.exec_refs 90277406 # number of memory reference insts executed +system.cpu.iew.exec_stores 23169669 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 231101 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 37116725 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 395719031 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 67044106 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3514925 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 278331746 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 453294 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 535171 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 104943598 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 227523 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 37082263 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 395310289 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 67107737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3518032 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 278329468 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 451527 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 13065 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23120513 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 520097 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 16343714 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.forwLoads 16336525 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 15761 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 35659 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 45746 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 48346210 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 16601009 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 371845968 # num instructions consuming a value -system.cpu.iew.wb_count 275965139 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.599241 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 34193 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 46033 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 48294008 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 16566547 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 34193 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 745041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2540542 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 371832293 # num instructions consuming a value +system.cpu.iew.wb_count 275994943 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.599268 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 222825226 # num instructions producing a value -system.cpu.iew.wb_rate 1.292148 # insts written-back per cycle -system.cpu.iew.wb_sent 277010234 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 516469209 # number of integer regfile reads -system.cpu.int_regfile_writes 283974364 # number of integer regfile writes -system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued +system.cpu.iew.wb_producers 222827233 # num instructions producing a value +system.cpu.iew.wb_rate 1.293815 # insts written-back per cycle +system.cpu.iew.wb_sent 277038754 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 516581259 # number of integer regfile reads +system.cpu.int_regfile_writes 284038520 # number of integer regfile writes +system.cpu.ipc 1.037710 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.037710 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 1197054 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187021337 66.36% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1590291 0.56% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68531630 24.32% 91.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23507188 8.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281846671 # Type of FU issued -system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 2813875 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 281847500 # Type of FU issued +system.cpu.iq.fp_alu_accesses 2638444 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5236518 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2534154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 5693561 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 2791850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009906 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67290 2.41% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2359047 84.50% 86.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 365513 13.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 564126820 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 395717604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 281846671 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1427 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 174039946 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 213480903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.320243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 280803852 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 774570053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 273460789 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 563268520 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 395308865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 281847500 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 173620640 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 90712 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 357064626 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 213229009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.321807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374231 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72462076 33.98% 33.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 65441995 30.69% 64.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36667606 17.20% 81.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20567003 9.65% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11965683 5.61% 97.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3990809 1.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1502036 0.70% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514117 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 117684 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 213480903 # Number of insts issued each cycle -system.cpu.iq.rate 1.319688 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency +system.cpu.iq.issued_per_cycle::total 213229009 # Number of insts issued each cycle +system.cpu.iq.rate 1.321250 # Inst issue rate +system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996171 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1561 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996171 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1561 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34292.872747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.872747 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 125580500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.634882 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_latency 53963500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48971000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5767 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2105 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 125572000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.634992 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113679000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634882 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 113677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634992 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency @@ -393,81 +393,82 @@ system.cpu.l2cache.Writeback_accesses 10 # nu system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.574468 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.574195 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34369.136512 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2112 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179510000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.712065 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5223 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 34367.438744 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2111 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179535500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.712202 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5224 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 162619000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.712065 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 162648000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.712202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5224 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.074157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2429.722700 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.074149 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34367.438744 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2112 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179510000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.712065 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5223 # number of overall misses +system.cpu.l2cache.overall_hits 2111 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179535500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.712202 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5224 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 162619000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.712065 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5223 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 162648000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.712202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2431.000786 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2106 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2430.737411 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2105 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 90499072 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30541649 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 104995800 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37116725 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 145140832 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 90595235 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30370608 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 104943598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37082263 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 145181965 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 213570763 # number of cpu cycles simulated +system.cpu.numCycles 213318781 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 18060003 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 18031749 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 21564374 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 74887260 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 1054491347 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 409882715 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 430914543 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 57380379 # Number of cycles rename is running -system.cpu.rename.SquashCycles 23161998 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 39968831 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 196551134 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 11087102 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 1043404245 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 22432 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 1444 # count of serializing insts renamed -system.cpu.rename.skidInsts 83221554 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 1312 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 583734688 # The number of ROB reads -system.cpu.rob.rob_writes 814640460 # The number of ROB writes -system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.IQFullEvents 21548402 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 74813235 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 16345466 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1053910938 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 409668647 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 430592677 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 57355298 # Number of cycles rename is running +system.cpu.rename.SquashCycles 23120513 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 39885814 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 196229268 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 11151271 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1042759667 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 22400 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed +system.cpu.rename.skidInsts 83004304 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1309 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 583086217 # The number of ROB reads +system.cpu.rob.rob_writes 813789002 # The number of ROB writes +system.cpu.timesIdled 1930 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- |