diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
| commit | d50d0152d0ea40e93c73dec1ffb6f37e79609fdd (patch) | |
| tree | c3e2400206e83dd3ca5f36a53ba5e88d31f26ac4 /tests/long/70.twolf/ref | |
| parent | 4b61abe8da876ed3e56a1851384ec11ede65bd89 (diff) | |
| download | gem5-d50d0152d0ea40e93c73dec1ffb6f37e79609fdd.tar.xz | |
ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
Diffstat (limited to 'tests/long/70.twolf/ref')
| -rw-r--r-- | tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini | 4 | ||||
| -rw-r--r-- | tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 14 |
2 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 28d94254f..0db8749b7 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -493,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 983eb9eea..cc80406fa 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53498 # Simulator instruction rate (inst/s) -host_mem_usage 259788 # Number of bytes of host memory used -host_seconds 3526.69 # Real time elapsed on the host -host_tick_rate 35668914 # Simulator tick rate (ticks/s) +host_inst_rate 145657 # Simulator instruction rate (inst/s) +host_mem_usage 262540 # Number of bytes of host memory used +host_seconds 1295.30 # Real time elapsed on the host +host_tick_rate 97115047 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188669132 # Number of instructions simulated sim_seconds 0.125793 # Number of seconds simulated @@ -288,7 +288,7 @@ system.cpu.iew.memOrderViolationEvents 222499 # Nu system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly system.cpu.int_regfile_reads 542109498 # number of integer regfile reads -system.cpu.int_regfile_writes 231159220 # number of integer regfile writes +system.cpu.int_regfile_writes 231159216 # number of integer regfile writes system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -490,8 +490,8 @@ system.cpu.memDep0.conflictingLoads 5314098 # Nu system.cpu.memDep0.conflictingStores 4016301 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 50338304 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 18109550 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 524567380 # number of misc regfile reads -system.cpu.misc_regfile_writes 825086 # number of misc regfile writes +system.cpu.misc_regfile_reads 524567378 # number of misc regfile reads +system.cpu.misc_regfile_writes 825084 # number of misc regfile writes system.cpu.numCycles 251586407 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |