diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/long/70.twolf/ref | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/long/70.twolf/ref')
5 files changed, 468 insertions, 464 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 0f49fe322..c38fd9b15 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:44:54 -M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip -M5 started Apr 10 2010 23:44:56 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:53:58 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3d8fcc484..bfc24ccd9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45830 # Simulator instruction rate (inst/s) -host_mem_usage 156280 # Number of bytes of host memory used -host_seconds 2005.28 # Real time elapsed on the host -host_tick_rate 49263361 # Simulator tick rate (ticks/s) +host_inst_rate 58773 # Simulator instruction rate (inst/s) +host_mem_usage 210528 # Number of bytes of host memory used +host_seconds 1563.70 # Real time elapsed on the host +host_tick_rate 63236927 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098787 # Number of seconds simulated -sim_ticks 98787075000 # Number of ticks simulated +sim_seconds 0.098884 # Number of seconds simulated +sim_ticks 98883816000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 5943749 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 9141724 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 5701477 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 8843835 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 1029596 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 11377435 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7465155 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 10240963 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 2255511 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 7985452 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.condIncorrect 11272469 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 7465254 # Number of conditional branches predicted +system.cpu.Branch-Predictor.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.lookups 10241221 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 2498039 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 7743182 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 64907308 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 78179 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 3313804 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.328521 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 195282323 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 267967 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 3261320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.328200 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 195278137 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 196150553 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 96.136450 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.instReqsProcessed 196150546 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 96.104408 # Percentage of cycles cpu is active system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.149810 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.149810 # CPI: Total CPI of All Threads +system.cpu.cpi 2.151916 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.151916 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51560 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48531.578947 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51575.789474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48548.421053 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24491000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24498500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23060500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56135.825713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53135.825713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56234.265734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53234.265734 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104356500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104539500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98779500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98962500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 129038000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 122023000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352013 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.845036 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352005 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.813640 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 129038000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121832000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 122023000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.845036 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.813640 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 103280491 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27107.378354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23969.601677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 103271695 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 238436500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 103175523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 27130.157283 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.529994 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 103166749 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 238040000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8796 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205803000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 8774 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205787000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8586 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 8585 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2500 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12027.916958 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12017.093652 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 103280491 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency -system.cpu.icache.demand_hits 103271695 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 238436500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 103175523 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency +system.cpu.icache.demand_hits 103166749 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 238040000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8796 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205803000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 8774 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205787000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8586 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 8585 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697585 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.655102 # Average occupied blocks per context -system.cpu.icache.overall_accesses 103280491 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.697574 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.631049 # Average occupied blocks per context +system.cpu.icache.overall_accesses 103175523 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 103271695 # number of overall hits -system.cpu.icache.overall_miss_latency 238436500 # number of overall miss cycles +system.cpu.icache.overall_hits 103166749 # number of overall hits +system.cpu.icache.overall_miss_latency 238040000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8796 # number of overall misses -system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205803000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 8774 # number of overall misses +system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205787000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8586 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 8585 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6752 # number of replacements -system.cpu.icache.sampled_refs 8586 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6751 # number of replacements +system.cpu.icache.sampled_refs 8585 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.655102 # Cycle average of tags in use -system.cpu.icache.total_refs 103271695 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.631049 # Cycle average of tags in use +system.cpu.icache.total_refs 103166749 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 103280490 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 7633377 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.465157 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.465157 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 103175522 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 7704221 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.464702 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.464702 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 103280539 # ITB accesses +system.cpu.itb.fetch_accesses 103175571 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 103280492 # ITB hits +system.cpu.itb.fetch_hits 103175524 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,28 +196,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52126.144165 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52230.263158 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91116500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 91298500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 9061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52164.544564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5998 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159780000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 9060 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52165.034280 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40019.915116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5997 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 159781500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338079 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 122581000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52220.720721 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52229.729730 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5796500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5797500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles @@ -227,73 +227,73 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.974917 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.974587 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5998 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 250896500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445092 # miss rate for demand accesses +system.cpu.l2cache.demand_accesses 10808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5997 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 251080000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.445133 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency 192511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.445133 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061820 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.061819 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2025.719647 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.727958 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 10809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2025.680452 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.727236 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 10808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5998 # number of overall hits -system.cpu.l2cache.overall_miss_latency 250896500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445092 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 5997 # number of overall hits +system.cpu.l2cache.overall_miss_latency 251080000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.445133 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4811 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445092 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency 192511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.445133 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2039.447605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5984 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2039.407688 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5983 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 197574151 # number of cpu cycles simulated -system.cpu.runCycles 189940774 # Number of cycles cpu stages are processed. +system.cpu.numCycles 197767633 # number of cpu cycles simulated +system.cpu.runCycles 190063412 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94293612 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 103280539 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 52.274318 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 105572319 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 92001832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.565723 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 104081667 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94592062 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 103175571 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 52.170100 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 105665019 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 92102614 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 46.571126 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 104275149 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.320200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 171037020 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.273906 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 171230502 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.431479 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 105671095 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.418339 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 105864577 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.515729 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 197574151 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.470221 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 197767633 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5dc5abaaf..0b7fa9656 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ce84b73e7..6a7caf9b4 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:07 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:45:37 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 96c3646b7..92d71f0ba 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80276 # Simulator instruction rate (inst/s) -host_mem_usage 196620 # Number of bytes of host memory used -host_seconds 1048.63 # Real time elapsed on the host -host_tick_rate 38925589 # Simulator tick rate (ticks/s) +host_inst_rate 153450 # Simulator instruction rate (inst/s) +host_mem_usage 210984 # Number of bytes of host memory used +host_seconds 548.58 # Real time elapsed on the host +host_tick_rate 73456175 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040819 # Number of seconds simulated -sim_ticks 40818658500 # Number of ticks simulated +sim_seconds 0.040297 # Number of seconds simulated +sim_ticks 40296654500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73457197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.251110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.949680 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 36278942 49.39% 49.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 18156304 24.72% 74.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 7455517 10.15% 84.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3880419 5.28% 89.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2046448 2.79% 92.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1301140 1.77% 94.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 721823 0.98% 95.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 760802 1.04% 96.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2855802 3.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 35335976 48.77% 48.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 18219580 25.15% 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 7350657 10.15% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3843959 5.31% 89.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2026400 2.80% 92.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1285963 1.77% 93.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 738665 1.02% 94.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 745593 1.03% 95.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73457197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2649.700000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 26497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356054 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1458.398369 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9171 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 29815560 # number of overall hits +system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9190 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use -system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use +system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31911121 # DTB accesses +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31794123 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31454022 # DTB hits -system.cpu.dtb.data_misses 457099 # DTB misses +system.cpu.dtb.data_hits 31394253 # DTB hits +system.cpu.dtb.data_misses 399870 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24718123 # DTB read accesses +system.cpu.dtb.read_accesses 24584547 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24262026 # DTB read hits -system.cpu.dtb.read_misses 456097 # DTB read misses -system.cpu.dtb.write_accesses 7192998 # DTB write accesses +system.cpu.dtb.read_hits 24185700 # DTB read hits +system.cpu.dtb.read_misses 398847 # DTB read misses +system.cpu.dtb.write_accesses 7209576 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7191996 # DTB write hits -system.cpu.dtb.write_misses 1002 # DTB write misses -system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched -system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2079596 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.055174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.061669 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7208553 # DTB write hits +system.cpu.dtb.write_misses 1023 # DTB write misses +system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched +system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 50560378 62.02% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 3114212 3.82% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2012618 2.47% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 3505366 4.30% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 4590613 5.63% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1506961 1.85% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 2028359 2.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1846743 2.27% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12363093 15.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency +system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses +system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.753902 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1543.991602 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19218965 # number of overall hits -system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_misses 11038 # number of overall misses -system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses +system.cpu.icache.overall_hits 19038605 # number of overall hits +system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses +system.cpu.icache.overall_misses 11140 # number of overall misses +system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8143 # number of replacements -system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8223 # number of replacements +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use -system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use +system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12812003 # Number of branches executed -system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate -system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7194632 # Number of stores executed +system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12897175 # Number of branches executed +system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate +system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7211217 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value -system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back +system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value +system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837672 # num instructions producing a value -system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle -system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65858228 # num instructions producing a value +system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle +system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64430040 61.93% 61.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 475055 0.46% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2782164 2.67% 65.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 115645 0.11% 65.18% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2377276 2.29% 67.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305748 0.29% 67.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755245 0.73% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25462424 24.48% 92.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7324714 7.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104028641 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 274346 14.19% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 31 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 6547 0.34% 14.53% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2333 0.12% 14.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 832912 43.09% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 743147 38.44% 96.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 73812 3.82% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% 43.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% 66.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% 80.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% 88.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% 95.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34420666 42.77% 42.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18632497 23.15% 65.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11734091 14.58% 80.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6720766 8.35% 88.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5079668 6.31% 95.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2378591 2.96% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1227784 1.53% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 245969 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate -system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate +system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19230073 # ITB accesses +system.cpu.itb.fetch_accesses 19049819 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19230003 # ITB hits -system.cpu.itb.fetch_misses 70 # ITB misses +system.cpu.itb.fetch_hits 19049745 # ITB hits +system.cpu.itb.fetch_misses 74 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,105 +343,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068091 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.205034 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.564546 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5110 # number of overall misses +system.cpu.l2cache.overall_hits 7254 # number of overall hits +system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5123 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 81637318 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 80593310 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed -system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- |