Update stats after elimination of Unallocated state.

Somehow ending threads with halt() instead of deallocate()
reduces the squash count on o3 by 1 (and a few other
similarly trivial changes).

3 files changed, 14 insertions, 14 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 6e7be67dd..7120f53fd 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -356,12 +356,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index dfd4eec8c..9b3fabe8e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr  8 2009 12:37:03
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
+M5 compiled Apr 14 2009 23:40:03
+M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
+M5 started Apr 14 2009 23:40:05
+M5 executing on phenom
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index e30cf0c3d..dce6864cd 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 205890                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211060                       # Number of bytes of host memory used
-host_seconds                                   408.86                       # Real time elapsed on the host
-host_tick_rate                               99836021                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 160619                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212880                       # Number of bytes of host memory used
+host_seconds                                   524.10                       # Real time elapsed on the host
+host_tick_rate                               77883837                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040819                       # Number of seconds simulated
@@ -20,9 +20,9 @@ system.cpu.commit.COM:branches               10240685                       # Nu
 system.cpu.commit.COM:bw_lim_events           2855802                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
 system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples     73457196                      
+system.cpu.commit.COM:committed_per_cycle.samples     73457197                      
 system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0     36278941   4938.79%           
+                               0     36278942   4938.79%           
                                1     18156304   2471.68%           
                                2      7455517   1014.95%           
                                3      3880419    528.26%           
@@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines                  19230003                       # Nu
 system.cpu.fetch.Cycles                      50198038                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.IcacheSquashes                519723                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                      167554902                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                 2079597                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                 2079596                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.branchRate                  0.238476                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles           19230003                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches           14728574                       # Number of branches that fetch has predicted taken