diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/70.twolf | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/70.twolf')
9 files changed, 1144 insertions, 1140 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index cbca14c5b..249041a4d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 43a475337..2583cc940 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,10 +3,12 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:49:49 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 30278595500 because target called exit() +122 123 124 Exiting @ tick 29167093500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 08d328376..f77f26233 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030279 # Number of seconds simulated -sim_ticks 30278595500 # Number of ticks simulated +sim_seconds 0.029167 # Number of seconds simulated +sim_ticks 29167093500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116969 # Simulator instruction rate (inst/s) -host_tick_rate 42072708 # Simulator tick rate (ticks/s) -host_mem_usage 256296 # Number of bytes of host memory used -host_seconds 719.67 # Real time elapsed on the host +host_inst_rate 127298 # Simulator instruction rate (inst/s) +host_tick_rate 44106983 # Simulator tick rate (ticks/s) +host_mem_usage 209296 # Number of bytes of host memory used +host_seconds 661.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25688278 # DTB read hits -system.cpu.dtb.read_misses 550762 # DTB read misses +system.cpu.dtb.read_hits 25236325 # DTB read hits +system.cpu.dtb.read_misses 540509 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26239040 # DTB read accesses -system.cpu.dtb.write_hits 7360758 # DTB write hits -system.cpu.dtb.write_misses 1044 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7361802 # DTB write accesses -system.cpu.dtb.data_hits 33049036 # DTB hits -system.cpu.dtb.data_misses 551806 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 33600842 # DTB accesses -system.cpu.itb.fetch_hits 19370237 # ITB hits -system.cpu.itb.fetch_misses 82 # ITB misses +system.cpu.dtb.read_accesses 25776834 # DTB read accesses +system.cpu.dtb.write_hits 7362909 # DTB write hits +system.cpu.dtb.write_misses 1032 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7363941 # DTB write accesses +system.cpu.dtb.data_hits 32599234 # DTB hits +system.cpu.dtb.data_misses 541541 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 33140775 # DTB accesses +system.cpu.itb.fetch_hits 18604047 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 19370319 # ITB accesses +system.cpu.itb.fetch_accesses 18604132 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 60557192 # number of cpu cycles simulated +system.cpu.numCycles 58334188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18972162 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14043194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1908534 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15684343 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12020738 # Number of BTB hits +system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1817403 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 20660360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 162109118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18972162 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13838141 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 29871214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8831306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3272537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 19370237 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 684277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.681098 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.259568 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 30592486 50.60% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2950542 4.88% 55.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2105012 3.48% 58.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3386904 5.60% 64.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4238557 7.01% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1492876 2.47% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1782148 2.95% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1645056 2.72% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12270119 20.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313293 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.676959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22547787 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2537266 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 28115662 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 618580 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6644405 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2987075 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13654 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 155918946 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42842 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6644405 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24245198 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 523469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 27028766 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2015831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148832808 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 266593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1498062 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 109279851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 192445710 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 181748286 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10697424 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40852490 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 518 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 515 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6036784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30729381 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9521294 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2640558 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 881343 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 123679327 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 494 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105899114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 512588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38384232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30395152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 105 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60463700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.751449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825920 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21057299 34.83% 34.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11707934 19.36% 54.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9587960 15.86% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925941 11.45% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5557420 9.19% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2847009 4.71% 95.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1835835 3.04% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796714 1.32% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147588 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60463700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186761 11.23% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 209 0.01% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6487 0.39% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3444 0.21% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845716 50.84% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 517920 31.13% 93.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103033 6.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 64090689 60.52% 60.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 486042 0.46% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799885 2.64% 63.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114989 0.11% 63.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411237 2.28% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311681 0.29% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763573 0.72% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27425152 25.90% 92.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7495540 7.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105899114 # Type of FU issued -system.cpu.iq.rate 1.748745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1663570 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015709 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 259207602 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 152594620 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93309235 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15230484 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9878183 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7072078 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 99520074 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8042603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1240194 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued +system.cpu.iq.rate 1.798857 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10733183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14770 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 472388 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3020191 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10319 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6644405 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16385 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 135563884 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 881728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30729381 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9521294 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 494 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 472388 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1792269 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 350241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2142510 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 103141866 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26239584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2757248 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11884063 # number of nop insts executed -system.cpu.iew.exec_refs 33601488 # number of memory reference insts executed -system.cpu.iew.exec_branches 12972684 # Number of branches executed -system.cpu.iew.exec_stores 7361904 # Number of stores executed -system.cpu.iew.exec_rate 1.703214 # Inst execution rate -system.cpu.iew.wb_sent 101639951 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 100381313 # cumulative count of insts written-back -system.cpu.iew.wb_producers 68069676 # num instructions producing a value -system.cpu.iew.wb_consumers 93955815 # num instructions consuming a value +system.cpu.iew.exec_nop 11799539 # number of nop insts executed +system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed +system.cpu.iew.exec_branches 12916232 # Number of branches executed +system.cpu.iew.exec_stores 7364040 # Number of stores executed +system.cpu.iew.exec_rate 1.754258 # Inst execution rate +system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67789343 # num instructions producing a value +system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.657628 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724486 # average fanout of values written-back +system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 43662883 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 53819295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.707623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.466902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24819499 46.12% 46.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11624197 21.60% 67.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5120039 9.51% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2844700 5.29% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1712935 3.18% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1498439 2.78% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 822147 1.53% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 790849 1.47% 91.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4586490 8.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 53819295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4586490 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 184797703 # The number of ROB reads -system.cpu.rob.rob_writes 277819902 # The number of ROB writes -system.cpu.timesIdled 2285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 180051805 # The number of ROB reads +system.cpu.rob.rob_writes 271380444 # The number of ROB writes +system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.719380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.719380 # CPI: Total CPI of All Threads -system.cpu.ipc 1.390086 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.390086 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 139300854 # number of integer regfile reads -system.cpu.int_regfile_writes 75996636 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185785 # number of floating regfile reads -system.cpu.fp_regfile_writes 6053506 # number of floating regfile writes -system.cpu.misc_regfile_reads 715599 # number of misc regfile reads +system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 138495671 # number of integer regfile reads +system.cpu.int_regfile_writes 75435014 # number of integer regfile writes +system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes +system.cpu.misc_regfile_reads 715554 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8657 # number of replacements -system.cpu.icache.tagsinuse 1596.063648 # Cycle average of tags in use -system.cpu.icache.total_refs 19358424 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1827.990935 # Average number of references to valid blocks. +system.cpu.icache.replacements 8695 # number of replacements +system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use +system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1596.063648 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779328 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 19358424 # number of ReadReq hits -system.cpu.icache.demand_hits 19358424 # number of demand (read+write) hits -system.cpu.icache.overall_hits 19358424 # number of overall hits -system.cpu.icache.ReadReq_misses 11813 # number of ReadReq misses -system.cpu.icache.demand_misses 11813 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11813 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188211000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 19370237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 19370237 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 19370237 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000610 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000610 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000610 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15932.531956 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15932.531956 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15932.531956 # average overall miss latency +system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses +system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124783500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000547 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000547 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000547 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11783.144476 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 156 # number of replacements -system.cpu.dcache.tagsinuse 1459.699326 # Cycle average of tags in use -system.cpu.dcache.total_refs 30929897 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2239 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13814.156766 # Average number of references to valid blocks. +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use +system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.699326 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24436799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 42 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30929855 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30929855 # number of overall hits -system.cpu.dcache.ReadReq_misses 922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8047 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8969 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8969 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27935000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289776500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 317711500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 317711500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24437721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30938824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30938824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.023256 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30298.264642 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36010.500808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35423.291337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35423.291337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,73 +410,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6731 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6731 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2238 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2238 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77915000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77915000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.023256 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32233.201581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35568.706697 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2399.023561 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7622 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.145833 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2381.411279 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.612282 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072675 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7611 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7636 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7636 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3486 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5193 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5193 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119743000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59251500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178994500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11097 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12829 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12829 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.314139 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985566 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.404786 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.404786 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.684452 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34710.896309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34468.419026 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34468.419026 # average overall miss latency +system.cpu.l2cache.demand_hits 7680 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7680 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3488 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119792500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59244000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 179036500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 179036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.403449 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.403449 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34469.869080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34469.869080 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5193 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5193 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108417500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53859000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162276500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162276500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.404786 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.404786 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100.831899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31551.845343 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 00b76845b..342457a8b 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index c549133d9..7a94cf61c 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 19:41:03 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -25,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 108225133500 because target called exit() +122 123 124 Exiting @ tick 105782426500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 0b4a9f9c5..9c02493cb 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.108225 # Number of seconds simulated -sim_ticks 108225133500 # Number of ticks simulated +sim_seconds 0.105782 # Number of seconds simulated +sim_ticks 105782426500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75904 # Simulator instruction rate (inst/s) -host_tick_rate 43540817 # Simulator tick rate (ticks/s) -host_mem_usage 267548 # Number of bytes of host memory used -host_seconds 2485.60 # Real time elapsed on the host -sim_insts 188667477 # Number of instructions simulated +host_inst_rate 104930 # Simulator instruction rate (inst/s) +host_tick_rate 58832155 # Simulator tick rate (ticks/s) +host_mem_usage 220996 # Number of bytes of host memory used +host_seconds 1798.04 # Real time elapsed on the host +sim_insts 188667447 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 216450268 # number of cpu cycles simulated +system.cpu.numCycles 211564854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103300495 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 81633853 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9933179 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 85260221 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79838053 # Number of BTB hits +system.cpu.BPredUnit.lookups 102102959 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80693522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9934423 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84198795 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79209656 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4770425 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 112925 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 45859797 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427202269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103300495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84608478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 110661906 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 34687559 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35479219 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4697254 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112889 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44543100 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 416703604 # Number of instructions fetch has processed +system.cpu.fetch.Branches 102102959 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83906910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 108778714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 33211132 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 34936553 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 779 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 41734734 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2307922 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 216391705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.142578 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 40617038 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2208646 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 211506610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137206 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647564 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 105933481 48.95% 48.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4813111 2.22% 51.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32934004 15.22% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18446280 8.52% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9282990 4.29% 79.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12615981 5.83% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8571229 3.96% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4380123 2.02% 91.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19414506 8.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102929819 48.67% 48.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4598020 2.17% 50.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32955527 15.58% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18221421 8.62% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9181259 4.34% 79.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12523238 5.92% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8470282 4.00% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4319419 2.04% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18307625 8.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 216391705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.477248 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.973674 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 54721006 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 34041868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102087484 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1309075 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24232272 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14250687 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 167114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 433129762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 697150 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 24232272 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63872072 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 611164 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28890421 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 94161740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4624036 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 397542070 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22398 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2387180 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 678079214 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1699552910 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1681277450 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18275460 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061696 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 380017513 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2786987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2738977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 24570466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 49895918 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 17636120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4759553 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2845254 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 339889742 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2325465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 265876001 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1090686 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 151055977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362148819 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 689877 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 216391705 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.228679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485743 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 211506610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.482608 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.969626 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53228641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 33488153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 100485702 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1214398 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23089716 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14176819 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166958 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 422710144 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 694356 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23089716 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62181422 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 455271 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28556828 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 92670031 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4553342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 388732639 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2224138 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 666278753 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1657677699 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1639787081 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17890618 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061648 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 368217100 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2705646 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2657641 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23338281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 46771972 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16999423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3794588 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2434419 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332719440 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2206649 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261972515 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1005249 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 143535623 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 342170938 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 571067 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 211506610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.238602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.491475 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 100636897 46.51% 46.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 38680237 17.88% 64.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34682486 16.03% 80.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22976662 10.62% 91.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11626624 5.37% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4959669 2.29% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2310222 1.07% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 416631 0.19% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 102277 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 97729672 46.21% 46.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37811383 17.88% 64.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34093128 16.12% 80.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22769109 10.77% 90.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11443716 5.41% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4778532 2.26% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2323194 1.10% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 402147 0.19% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 155729 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 216391705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 211506610 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 400224 18.78% 18.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5529 0.26% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 59 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 41 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1248313 58.57% 77.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 477105 22.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 397392 17.88% 17.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5524 0.25% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 43 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1333839 60.01% 78.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 485736 21.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 206820187 77.79% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928873 0.35% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 5969 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33098 0.01% 78.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166620 0.06% 78.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 261178 0.10% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76402 0.03% 78.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 472124 0.18% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207762 0.08% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71816 0.03% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 326 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 42647461 16.04% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14184185 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 205005652 78.25% 78.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928362 0.35% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 5862 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33106 0.01% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166621 0.06% 78.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 256879 0.10% 78.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76399 0.03% 78.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467584 0.18% 78.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207638 0.08% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71818 0.03% 79.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 328 0.00% 79.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 40692198 15.53% 94.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14060068 5.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 265876001 # Type of FU issued -system.cpu.iq.rate 1.228347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2131272 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008016 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 747569642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 491340043 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 245818526 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3796023 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2315934 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1850284 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266096231 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1911042 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1286575 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261972515 # Type of FU issued +system.cpu.iq.rate 1.238261 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2222588 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008484 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 734922033 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 476231649 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242866615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3757444 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2242269 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1844486 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262305042 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1890061 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 20044239 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9909 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 389239 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4989293 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16920299 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31179 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12638 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4352602 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24232272 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29384 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2101 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342268798 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4011941 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 49895918 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 17636120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2301609 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 367 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1495 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 389239 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10042133 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1698405 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11740538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 252918304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 40460736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12957697 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23089716 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13717 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1061 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334979671 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3743340 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 46771972 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16999423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2182801 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12638 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9998550 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1696549 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11695099 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 249247765 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 38548373 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12724750 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53591 # number of nop insts executed -system.cpu.iew.exec_refs 54201060 # number of memory reference insts executed -system.cpu.iew.exec_branches 52956495 # Number of branches executed -system.cpu.iew.exec_stores 13740324 # Number of stores executed -system.cpu.iew.exec_rate 1.168482 # Inst execution rate -system.cpu.iew.wb_sent 249352337 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 247668810 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150626342 # num instructions producing a value -system.cpu.iew.wb_consumers 251613909 # num instructions consuming a value +system.cpu.iew.exec_nop 53582 # number of nop insts executed +system.cpu.iew.exec_refs 52189835 # number of memory reference insts executed +system.cpu.iew.exec_branches 52589546 # Number of branches executed +system.cpu.iew.exec_stores 13641462 # Number of stores executed +system.cpu.iew.exec_rate 1.178115 # Inst execution rate +system.cpu.iew.wb_sent 246271273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 244711101 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148454614 # num instructions producing a value +system.cpu.iew.wb_consumers 247957784 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.144230 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598641 # average fanout of values written-back +system.cpu.iew.wb_rate 1.156672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598709 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188681865 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 153577683 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635588 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9794361 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 192159434 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.981903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.655341 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681835 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146288700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635582 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9795726 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 188416895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.001406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.682967 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108154489 56.28% 56.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41572533 21.63% 77.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19548903 10.17% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8803666 4.58% 92.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5118368 2.66% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2098797 1.09% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1631204 0.85% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1005945 0.52% 97.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4225529 2.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 105298145 55.89% 55.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 40798709 21.65% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19462081 10.33% 87.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8761911 4.65% 92.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4909468 2.61% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2009419 1.07% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1710426 0.91% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008180 0.54% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4458556 2.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 192159434 # Number of insts commited each cycle -system.cpu.commit.count 188681865 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 188416895 # Number of insts commited each cycle +system.cpu.commit.count 188681835 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498505 # Number of memory references committed -system.cpu.commit.loads 29851678 # Number of loads committed +system.cpu.commit.refs 42498493 # Number of memory references committed +system.cpu.commit.loads 29851672 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283876 # Number of branches committed +system.cpu.commit.branches 40283870 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150114997 # Number of committed integer instructions. +system.cpu.commit.int_insts 150114973 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4225529 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4458556 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 530188252 # The number of ROB reads -system.cpu.rob.rob_writes 708816282 # The number of ROB writes -system.cpu.timesIdled 1726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58563 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667477 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667477 # Number of Instructions Simulated -system.cpu.cpi 1.147258 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.147258 # CPI: Total CPI of All Threads -system.cpu.ipc 0.871644 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.871644 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1130629656 # number of integer regfile reads -system.cpu.int_regfile_writes 411782000 # number of integer regfile writes -system.cpu.fp_regfile_reads 2929902 # number of floating regfile reads -system.cpu.fp_regfile_writes 2506543 # number of floating regfile writes -system.cpu.misc_regfile_reads 516287293 # number of misc regfile reads -system.cpu.misc_regfile_writes 824422 # number of misc regfile writes -system.cpu.icache.replacements 1945 # number of replacements -system.cpu.icache.tagsinuse 1331.549144 # Cycle average of tags in use -system.cpu.icache.total_refs 41730466 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3654 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11420.488779 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 518923673 # The number of ROB reads +system.cpu.rob.rob_writes 693093847 # The number of ROB writes +system.cpu.timesIdled 1715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667447 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667447 # Number of Instructions Simulated +system.cpu.cpi 1.121364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.121364 # CPI: Total CPI of All Threads +system.cpu.ipc 0.891771 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.891771 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1112037925 # number of integer regfile reads +system.cpu.int_regfile_writes 407325224 # number of integer regfile writes +system.cpu.fp_regfile_reads 2928951 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497682 # number of floating regfile writes +system.cpu.misc_regfile_reads 502867512 # number of misc regfile reads +system.cpu.misc_regfile_writes 824410 # number of misc regfile writes +system.cpu.icache.replacements 1940 # number of replacements +system.cpu.icache.tagsinuse 1334.073699 # Cycle average of tags in use +system.cpu.icache.total_refs 40612809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3646 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11139.004114 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1331.549144 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.650170 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41730466 # number of ReadReq hits -system.cpu.icache.demand_hits 41730466 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41730466 # number of overall hits -system.cpu.icache.ReadReq_misses 4268 # number of ReadReq misses -system.cpu.icache.demand_misses 4268 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4268 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101918000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101918000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101918000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41734734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41734734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41734734 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23879.568885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23879.568885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23879.568885 # average overall miss latency +system.cpu.icache.occ_blocks::0 1334.073699 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.651403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 40612809 # number of ReadReq hits +system.cpu.icache.demand_hits 40612809 # number of demand (read+write) hits +system.cpu.icache.overall_hits 40612809 # number of overall hits +system.cpu.icache.ReadReq_misses 4229 # number of ReadReq misses +system.cpu.icache.demand_misses 4229 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4229 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101377500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101377500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101377500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 40617038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 40617038 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 40617038 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23971.979191 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23971.979191 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23971.979191 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 614 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 614 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 614 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3654 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3654 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3654 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3646 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3646 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3646 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74785000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74785000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74785000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74805000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74805000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74805000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20466.611932 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20517.004937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1408.919446 # Cycle average of tags in use -system.cpu.dcache.total_refs 50759192 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27407.771058 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1408.142162 # Cycle average of tags in use +system.cpu.dcache.total_refs 48578921 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1851 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 26244.689897 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.919446 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343974 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 38350065 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27780 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 50706812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 50706812 # number of overall hits -system.cpu.dcache.ReadReq_misses 1815 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.142162 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343785 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 36170054 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356741 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27532 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 48526795 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 48526795 # number of overall hits +system.cpu.dcache.ReadReq_misses 1787 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7546 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9355 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9355 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59756000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236779500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9333 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9333 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59024500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236727000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 296535500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 296535500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 38351880 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 295751500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 295751500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 36171841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24600 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 50716167 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 50716167 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 27534 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24594 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 48536128 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 48536128 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000184 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000184 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32923.415978 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31403.116711 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.000073 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000192 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000192 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33029.938444 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31371.190034 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31698.075895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31698.075895 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31688.792457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31688.792457 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1051 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6452 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 19 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1026 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1852 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7482 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7482 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1090 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1851 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1851 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24358000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62603500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62603500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24308000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62630000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62630000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31882.198953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35152.113971 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.181340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35157.798165 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1935.489256 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1725 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2688 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.641741 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1934.153388 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2689 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.637412 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1932.435208 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054049 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058973 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1931.095297 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.058091 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058932 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1725 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 19 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1734 # number of overall hits +system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1723 # number of overall hits system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1079 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3772 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3772 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92325500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37082000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129407500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129407500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1088 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5506 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5506 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.609552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991728 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.685071 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.685071 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34283.512811 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34367.006487 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34307.396607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34307.396607 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3774 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3774 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129478000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 19 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5497 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5497 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.611073 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.991743 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.686556 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.686556 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34279.985147 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34377.428307 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34307.896131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34307.896131 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2680 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1079 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3759 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3760 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3760 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83299500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33503500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116803000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116803000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83267000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33562000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116829000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116829000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991728 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.682710 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.682710 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.902985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607897 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.684009 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.684009 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.373647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31047.178538 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 5bb467c35..8802a5811 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 7a3f808a7..f7d229ce0 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,10 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 17:25:41 -gem5 started Aug 17 2011 17:43:51 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 99831779000 because target called exit() +122 123 124 Exiting @ tick 96610526000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 21b77f826..43a8220e5 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.099832 # Number of seconds simulated -sim_ticks 99831779000 # Number of ticks simulated +sim_seconds 0.096611 # Number of seconds simulated +sim_ticks 96610526000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87193 # Simulator instruction rate (inst/s) -host_tick_rate 39323014 # Simulator tick rate (ticks/s) -host_mem_usage 268152 # Number of bytes of host memory used -host_seconds 2538.76 # Real time elapsed on the host +host_inst_rate 102112 # Simulator instruction rate (inst/s) +host_tick_rate 44565176 # Simulator tick rate (ticks/s) +host_mem_usage 220868 # Number of bytes of host memory used +host_seconds 2167.85 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 199663559 # number of cpu cycles simulated +system.cpu.numCycles 193221053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26033375 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 26033375 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892272 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23801635 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21124617 # Number of BTB hits +system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31432261 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 264493397 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26033375 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 21124617 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 71518034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27440776 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72430048 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 173 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 29258071 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 583239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 199575786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.208704 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129959453 65.12% 65.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4150455 2.08% 67.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3286315 1.65% 68.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4425223 2.22% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4327377 2.17% 73.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4568651 2.29% 75.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5572926 2.79% 78.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3068408 1.54% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 40216978 20.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 199575786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130386 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45674333 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62083287 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 57427578 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10196895 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24193693 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 428380569 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24193693 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54435501 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16645801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21737 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 58104790 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46174264 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 415835044 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 22459451 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 21291992 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 441873091 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1077088979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1065665407 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11423572 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 207509682 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1829 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1823 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98204521 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105334480 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37821412 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 75455534 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24783352 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 400833570 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 286380326 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 245766 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 179000562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 366769994 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 581 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 199575786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.434945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.451491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64436357 32.29% 32.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 57784347 28.95% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35429830 17.75% 78.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21049464 10.55% 89.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13197205 6.61% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5079102 2.54% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1923482 0.96% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 545287 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130712 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 199575786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 94614 3.23% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2515029 85.77% 88.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322713 11.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1207901 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187612443 65.51% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1650340 0.58% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 71566969 24.99% 91.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24342673 8.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 286380326 # Type of FU issued -system.cpu.iq.rate 1.434314 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2932356 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010239 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770019302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 574569480 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277218966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5495258 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5820238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2640122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 285339093 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2765688 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17496370 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued +system.cpu.iq.rate 1.488870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48684890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 567154 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17305696 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45677 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24193693 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 457791 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 303468 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 400835397 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134633 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105334480 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37821412 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1827 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 212810 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14667 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 567154 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2502429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 590366 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092795 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 282646911 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 70091222 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3733415 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 93958027 # number of memory reference insts executed -system.cpu.iew.exec_branches 15691329 # Number of branches executed -system.cpu.iew.exec_stores 23866805 # Number of stores executed -system.cpu.iew.exec_rate 1.415616 # Inst execution rate -system.cpu.iew.wb_sent 281113586 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 279859088 # cumulative count of insts written-back -system.cpu.iew.wb_producers 226653177 # num instructions producing a value -system.cpu.iew.wb_consumers 377782482 # num instructions consuming a value +system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed +system.cpu.iew.exec_branches 15668383 # Number of branches executed +system.cpu.iew.exec_stores 24050878 # Number of stores executed +system.cpu.iew.exec_rate 1.469089 # Inst execution rate +system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227942764 # num instructions producing a value +system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401653 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599957 # average fanout of values written-back +system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179482154 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892451 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 175382093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.262176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.674972 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66614816 37.98% 37.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 64778126 36.94% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16236292 9.26% 84.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12183178 6.95% 91.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5701402 3.25% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3006065 1.71% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2037233 1.16% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1096406 0.63% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3728575 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 175382093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3728575 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572498689 # The number of ROB reads -system.cpu.rob.rob_writes 825932723 # The number of ROB writes -system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 87773 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561772958 # The number of ROB reads +system.cpu.rob.rob_writes 817171098 # The number of ROB writes +system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.901973 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.901973 # CPI: Total CPI of All Threads -system.cpu.ipc 1.108680 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.108680 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 526429192 # number of integer regfile reads -system.cpu.int_regfile_writes 287807377 # number of integer regfile writes -system.cpu.fp_regfile_reads 3610412 # number of floating regfile reads -system.cpu.fp_regfile_writes 2295659 # number of floating regfile writes -system.cpu.misc_regfile_reads 148624711 # number of misc regfile reads +system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads +system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 530742767 # number of integer regfile reads +system.cpu.int_regfile_writes 288972647 # number of integer regfile writes +system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads +system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes +system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4242 # number of replacements -system.cpu.icache.tagsinuse 1597.360420 # Cycle average of tags in use -system.cpu.icache.total_refs 29250473 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6209 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4710.979707 # Average number of references to valid blocks. +system.cpu.icache.replacements 4235 # number of replacements +system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use +system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.360420 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779961 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 29250474 # number of ReadReq hits -system.cpu.icache.demand_hits 29250474 # number of demand (read+write) hits -system.cpu.icache.overall_hits 29250474 # number of overall hits -system.cpu.icache.ReadReq_misses 7597 # number of ReadReq misses -system.cpu.icache.demand_misses 7597 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7597 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 175067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 175067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 175067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 29258071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 29258071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 29258071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23044.293800 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23044.293800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23044.293800 # average overall miss latency +system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits +system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28839309 # number of overall hits +system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses +system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7555 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1135 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1135 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1135 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6462 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6462 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6462 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125815000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19469.978335 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 58 # number of replacements -system.cpu.dcache.tagsinuse 1414.389130 # Cycle average of tags in use -system.cpu.dcache.total_refs 72873832 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1985 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36712.257935 # Average number of references to valid blocks. +system.cpu.dcache.replacements 59 # number of replacements +system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use +system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1414.389130 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345310 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52365835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20507475 # number of WriteReq hits -system.cpu.dcache.demand_hits 72873310 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72873310 # number of overall hits -system.cpu.dcache.ReadReq_misses 884 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8255 # number of WriteReq misses -system.cpu.dcache.demand_misses 9139 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9139 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27524500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 227342500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 254867000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 254867000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52366719 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits +system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 73596113 # number of overall hits +system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses +system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72882449 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72882449 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31136.312217 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27539.975772 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27887.843309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27887.843309 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 460 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6439 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6899 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6899 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1816 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 63530000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77603500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77603500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33192.216981 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34983.480176 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2508.886918 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2866 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3770 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.760212 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2507.064055 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.822864 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076510 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000056 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2865 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2873 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2873 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3766 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 253 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53203000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 182169500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 182169500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2874 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 253 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1564 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8195 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8195 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.567938 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994885 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.649420 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.649420 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34244.954859 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.159383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34229.518978 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34229.518978 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3766 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 253 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5322 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116813500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7843000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48344500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 165158000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 165158000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567938 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.649420 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.649420 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.923526 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.730077 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |