tests: update tests for TLB unification

21 files changed, 148 insertions, 106 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 6fbd6e595..6e7be67dd 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 4f595ede7..dfd4eec8c 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:16:08
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:37:03
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 21c5777d8..e30cf0c3d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 205423                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211084                       # Number of bytes of host memory used
-host_seconds                                   409.79                       # Real time elapsed on the host
-host_tick_rate                               99609545                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 205890                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211060                       # Number of bytes of host memory used
+host_seconds                                   408.86                       # Real time elapsed on the host
+host_tick_rate                               99836021                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040819                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles           29917869                       # Nu
 system.cpu.decode.DECODE:SquashCycles         8071146                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts          45156                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles         189170                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                      31911121                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          31454022                       # DTB hits
-system.cpu.dtb.misses                          457099                       # DTB misses
+system.cpu.dtb.data_accesses                 31911121                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     31454022                       # DTB hits
+system.cpu.dtb.data_misses                     457099                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 24718123                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     24262026                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined        50669408                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            244059                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     47385393                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      19230073                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          19230003                       # ITB hits
-system.cpu.itb.misses                              70                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                19230073                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    19230003                       # ITB hits
+system.cpu.itb.fetch_misses                        70                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1735                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017                       # average ReadExReq mshr miss latency
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 593992332..1107790b1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index d3d15e406..68a75cbd9 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:41:19
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:36:46
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index bce09d7dd..bf89ff397 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5743124                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200524                       # Number of bytes of host memory used
-host_seconds                                    16.00                       # Real time elapsed on the host
-host_tick_rate                             2871531471                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5529646                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202292                       # Number of bytes of host memory used
+host_seconds                                    16.62                       # Real time elapsed on the host
+host_tick_rate                             2764786682                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.045952                       # Number of seconds simulated
 sim_ticks                                 45951567500                       # Number of ticks simulated
-system.cpu.dtb.accesses                      26497334                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          26497301                       # DTB hits
-system.cpu.dtb.misses                              33                       # DTB misses
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     19996198                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                     6501103                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      91903136                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          91903089                       # ITB hits
-system.cpu.itb.misses                              47                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                91903136                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    91903089                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index b166b9052..2164626a2 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index c9ffcf959..24227ac66 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:41:35
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py long/70.twolf/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:33:56
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index c77e086b4..e5dfef14d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2902114                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207972                       # Number of bytes of host memory used
-host_seconds                                    31.67                       # Real time elapsed on the host
-host_tick_rate                             3749775750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2783619                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209832                       # Number of bytes of host memory used
+host_seconds                                    33.02                       # Real time elapsed on the host
+host_tick_rate                             3596666384                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118747                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               1442.022508                       # Cy
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
-system.cpu.dtb.accesses                      26497334                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          26497301                       # DTB hits
-system.cpu.dtb.misses                              33                       # DTB misses
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     19996198                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                 91894580                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      91903137                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          91903090                       # ITB hits
-system.cpu.itb.misses                              47                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                91903137                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    91903090                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 3d5e2c242..a9a96bdd5 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index eb6462de2..bcecb77e1 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:55:15
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py long/70.twolf/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:32:55
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 9b4c86591..2a0d5ef75 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2406877                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202316                       # Number of bytes of host memory used
-host_seconds                                    80.37                       # Real time elapsed on the host
-host_tick_rate                             1203441627                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3173092                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204068                       # Number of bytes of host memory used
+host_seconds                                    60.96                       # Real time elapsed on the host
+host_tick_rate                             1586549351                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 65aeb1d48..1c4d82608 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index b27d83682..bc529416a 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:33:08
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:31:47
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index f73a0dcbf..1993c7752 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 732316                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209324                       # Number of bytes of host memory used
-host_seconds                                   264.15                       # Real time elapsed on the host
-host_tick_rate                             1024317022                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1944755                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211604                       # Number of bytes of host memory used
+host_seconds                                    99.47                       # Real time elapsed on the host
+host_tick_rate                             2720193548                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270578                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index d0a878165..e88047c7b 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 100c59b7e..cba3e283b 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:54:15
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:58:24
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index f3c94835b..d349a3ec1 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 744144                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204416                       # Number of bytes of host memory used
-host_seconds                                   293.75                       # Real time elapsed on the host
-host_tick_rate                              442578451                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2597593                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206992                       # Number of bytes of host memory used
+host_seconds                                    84.15                       # Real time elapsed on the host
+host_tick_rate                             1544910141                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   218595300                       # Number of instructions simulated
 sim_seconds                                  0.130009                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index c231a2f5e..8b6664da9 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 2a43627aa..71a382614 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:58:47
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:09:44
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 3d7cbb069..06ac4f668 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 660588                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211972                       # Number of bytes of host memory used
-host_seconds                                   330.91                       # Real time elapsed on the host
-host_tick_rate                              758349031                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1718028                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214564                       # Number of bytes of host memory used
+host_seconds                                   127.24                       # Real time elapsed on the host
+host_tick_rate                             1972277446                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   218595300                       # Number of instructions simulated
 sim_seconds                                  0.250945                       # Number of seconds simulated